gates.ref

来自「openaccess与verilog互相转化时所用的源代码」· REF 代码 · 共 218 行

REF
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******************************************************************************* No Explode, No EMH******************************************************************************Warning: Gate instantiations are not implementedWarning: Gate instantiations are not implementedWarning: Gate instantiations are not implementedWarning: Gate instantiations are not implementedWarning: Gate instantiations are not implementedWarning: Gate instantiations are not implementedWarning: Gate instantiations are not implementedWarning: Gate instantiations are not implementedWarning: Gate instantiations are not implementedWarning: Gate instantiations are not implementedWarning: Gate instantiations are not implementedWarning: Gate instantiations are not implementedWarning: Gate instantiations are not implementedWarning: Gate instantiations are not implementedWarning: Gate instantiations are not implementedWarning: Gate instantiations are not implementedWarning: Gate instantiations are not implementedWarning: Gate instantiations are not implementedWarning: Gate instantiations are not implementedWarning: Gate instantiations are not implementedWarning: Gate instantiations are not implementedWarning: Gate instantiations are not implementedWarning: Gate instantiations are not implementedWarning: Gate instantiations are not implementedContents of gates_design.top.netlist    Contents of TOP module top            Term: 'in1' (ModScalarTerm)        	TermType:	input        	NumBits:	1        	Net:		'in1'        	Position:	0            Term: 'in2' (ModScalarTerm)        	TermType:	input        	NumBits:	1        	Net:		'in2'        	Position:	1            Term: 'in3' (ModScalarTerm)        	TermType:	input        	NumBits:	1        	Net:		'in3'        	Position:	2            Term: 'in4' (ModScalarTerm)        	TermType:	input        	NumBits:	1        	Net:		'in4'        	Position:	3            Term: 'out1' (ModScalarTerm)        	TermType:	output        	NumBits:	1        	Net:		'out1'        	Position:	4            Term: 'out2' (ModScalarTerm)        	TermType:	output        	NumBits:	1        	Net:		'out2'        	Position:	5            Term: 'out3' (ModScalarTerm)        	TermType:	output        	NumBits:	1        	Net:		'out3'        	Position:	6            Term: 'out4' (ModScalarTerm)        	TermType:	output        	NumBits:	1        	Net:		'out4'        	Position:	7            Term: 'io1' (ModScalarTerm)        	TermType:	inputOutput        	NumBits:	1        	Net:		'io1'        	Position:	8            Term: 'io2' (ModScalarTerm)        	TermType:	inputOutput        	NumBits:	1        	Net:		'io2'        	Position:	9            Term: 'en1' (ModScalarTerm)        	TermType:	inputOutput        	NumBits:	1        	Net:		'en1'        	Position:	10            Term: 'en2' (ModScalarTerm)        	TermType:	inputOutput        	NumBits:	1        	Net:		'en2'        	Position:	11            Net: 'in1' (ModScalarNet)            Net: 'in2' (ModScalarNet)            Net: 'in3' (ModScalarNet)            Net: 'in4' (ModScalarNet)            Net: 'out1' (ModScalarNet)            Net: 'out2' (ModScalarNet)            Net: 'out3' (ModScalarNet)            Net: 'out4' (ModScalarNet)            Net: 'io1' (ModScalarNet)            Net: 'io2' (ModScalarNet)            Net: 'en1' (ModScalarNet)            Net: 'en2' (ModScalarNet)Reader succeeded******************************************************************************* No Explode, EMH******************************************************************************Warning: Gate instantiations are not implementedWarning: Gate instantiations are not implementedWarning: Gate instantiations are not implementedWarning: Gate instantiations are not implementedWarning: Gate instantiations are not implementedWarning: Gate instantiations are not implementedWarning: Gate instantiations are not implementedWarning: Gate instantiations are not implementedWarning: Gate instantiations are not implementedWarning: Gate instantiations are not implementedWarning: Gate instantiations are not implementedWarning: Gate instantiations are not implementedWarning: Gate instantiations are not implementedWarning: Gate instantiations are not implementedWarning: Gate instantiations are not implementedWarning: Gate instantiations are not implementedWarning: Gate instantiations are not implementedWarning: Gate instantiations are not implementedWarning: Gate instantiations are not implementedWarning: Gate instantiations are not implementedWarning: Gate instantiations are not implementedWarning: Gate instantiations are not implementedWarning: Gate instantiations are not implementedWarning: Gate instantiations are not implementedInfo: The top module is topContents of gates_designEMH.top.netlist    Contents of TOP module top            Term: 'in1' (ModScalarTerm)        	TermType:	input        	NumBits:	1        	Net:		'in1'        	Position:	0            Term: 'in2' (ModScalarTerm)        	TermType:	input        	NumBits:	1        	Net:		'in2'        	Position:	1            Term: 'in3' (ModScalarTerm)        	TermType:	input        	NumBits:	1        	Net:		'in3'        	Position:	2            Term: 'in4' (ModScalarTerm)        	TermType:	input        	NumBits:	1        	Net:		'in4'        	Position:	3            Term: 'out1' (ModScalarTerm)        	TermType:	output        	NumBits:	1        	Net:		'out1'        	Position:	4            Term: 'out2' (ModScalarTerm)        	TermType:	output        	NumBits:	1        	Net:		'out2'        	Position:	5            Term: 'out3' (ModScalarTerm)        	TermType:	output        	NumBits:	1        	Net:		'out3'        	Position:	6            Term: 'out4' (ModScalarTerm)        	TermType:	output        	NumBits:	1        	Net:		'out4'        	Position:	7            Term: 'io1' (ModScalarTerm)        	TermType:	inputOutput        	NumBits:	1        	Net:		'io1'        	Position:	8            Term: 'io2' (ModScalarTerm)        	TermType:	inputOutput        	NumBits:	1        	Net:		'io2'        	Position:	9            Term: 'en1' (ModScalarTerm)        	TermType:	inputOutput        	NumBits:	1        	Net:		'en1'        	Position:	10            Term: 'en2' (ModScalarTerm)        	TermType:	inputOutput        	NumBits:	1        	Net:		'en2'        	Position:	11            Net: 'in1' (ModScalarNet)            Net: 'in2' (ModScalarNet)            Net: 'in3' (ModScalarNet)            Net: 'in4' (ModScalarNet)            Net: 'out1' (ModScalarNet)            Net: 'out2' (ModScalarNet)            Net: 'out3' (ModScalarNet)            Net: 'out4' (ModScalarNet)            Net: 'io1' (ModScalarNet)            Net: 'io2' (ModScalarNet)            Net: 'en1' (ModScalarNet)            Net: 'en2' (ModScalarNet)Reader succeeded

gates.ref - 源码说明

本页面展示了「openaccess与verilog互相转化时所用的源代码」中的 gates.ref 源码文件，采用 REF 编程语言编写，共 218 行代码。您可以在线阅读完整代码内容，也可以返回资源详情页下载完整源码包进行本地学习和开发。

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