badorderleaf1.v

来自「openaccess与verilog互相转化时所用的源代码」· Verilog 代码 · 共 15 行

// The terminals of the scalarLeaf module are declared inconsistently
// with the actual leaf cell.



module scalarLeaf (output out, input in);
endmodule



module top();
    wire a, b;
    scalarLeaf  I1(a, b);
endmodule