stuborder.v

来自「openaccess与verilog互相转化时所用的源代码」· Verilog 代码 · 共 12 行

// This test is similar to the stub.v test, except connect by order is 
// used and the width of the net connecting at position 2 is incorrect.

module top();
    wire            wireToX, wireToZ;
    wire    [1:0]   busToY;
    
    stub   named(.x(wireToX), .z(wireToZ));
    stub   order(wireToX, busToY, wireToZ);
endmodule