widthmismatch.v

来自「openaccess与verilog互相转化时所用的源代码」· Verilog 代码 · 共 19 行

// This test verifies that the reader will catch width mismatches between 
// the terminals on a vector instance and a net.  This test uses connect by
// name.



module child(input [1:0] a, output b);
endmodule



module top();
    wire [7:0] x;
    wire y;
    
    child I1[0:1](.a(x), .b(y));
    
endmodule