globalconn.v

来自「openaccess与verilog互相转化时所用的源代码」· Verilog 代码 · 共 27 行

module globals;
    wire globalNet;
endmodule



module level1(input [31:0]  l1_in,
	      output        l1_out);
 	reg l1_reg;
endmodule

module level2A(inout [1:0] l2Aio);
	level1 I1(1, globals.globalNet);
endmodule


module level2B(inout [1:0] l2Bio);
	level1 I1('h80000000, globals.globalNet);
endmodule


module top;
	level2A I1A(2'b10);
	level2B I2B(2'b01);
endmodule