pcr782725.v

来自「openaccess与verilog互相转化时所用的源代码」· Verilog 代码 · 共 27 行

// In this test case outvcc1 is declared as a supply1 but it has already been 
// declared as the net connected to one of the output terminals. All the other 
// nets declared as supply1 have never been explicitly created. The sigType of
// outvcc1 should be updated to be TieHigh.  Note that it should NOT be set 
// equivalent to tie1 because that would defeat the purpose of porting the
// signal.

module top( in, out, outvcc1, outvcc2, outvccbus );
	input  in;
	output out; 
	output outvcc1, outvcc2;
	output[1:3] outvccbus;

	wire[1:3] vccbus;

	supply1 outvcc1;
	assign  outvcc2 = 1'b1;
	supply1 outvccbus[2];
	assign  outvccbus[3] = 1'b1;

	supply1 vcc1 ;
	assign  vcc2 = 1'b1;
	supply1 vccbus[2];
	assign  vccbus[3] = 1'b1;
endmodule