multifile3.v

来自「openaccess与verilog互相转化时所用的源代码」· Verilog 代码 · 共 13 行

// This is the third of three files in the multiFile test.

module top();

	reg        scalar1,scalar2,scalar3;
	reg [1:0]  bus1,bus2,bus3;  

	level3 I1(scalar1,bus1),
	       I2(scalar2,bus2),
	       I3(scalar3,bus3);

endmodule