unconnected.ref

openaccess与verilog互相转化时所用的源代码

// Verilog file for cell "top" view "netlist" 
// Language Version: 2001 

module leaf (
    in,
    out);

    input [3:0] in;
    output [3:0] out;

endmodule // leaf


module top ();

    wire N__0;
    wire N__1;

    leaf I__0 (
            .in({UNCONNECTED_oaVerilogIn0_,UNCONNECTED_oaVerilogIn1_,N__0,UNCONNECTED_oaVerilogIn2_}),
            .out({UNCONNECTED_oaVerilogIn3_,UNCONNECTED_oaVerilogIn4_,UNCONNECTED_oaVerilogIn5_,N__1}));
endmodule // top