redef.v

来自「openaccess与verilog互相转化时所用的源代码」· Verilog 代码 · 共 23 行

// Verify that the reader can handle module redefinitions within the same
// input file. The xyz module is defined twice and has different contents in 
// each definition. The second definintion should win.

module leaf(input in, output out);
endmodule

module xyz (input a, output b);
    leaf    I1(.in(a), .out(b));
endmodule

// This module should win.
module xyz (input a, output b);
    wire c;
	
    leaf    I1(.in(a), .out(c));
    leaf    I2(.in(c), .out(b));
endmodule

module top ();
    xyz u0 (x, y);
endmodule