existing.v

来自「openaccess与verilog互相转化时所用的源代码」· Verilog 代码 · 共 10 行

// Test the reader's behavior when operating on an existing design.

module leaf(input in, output out);
endmodule

module existing(input in, output out, inout t, inout aux);
    leaf extra(in, out);
endmodule