oaverilogannotate.h

来自「openaccess与verilog互相转化时所用的源代码」· C头文件 代码 · 共 76 行

// *****************************************************************************
// *****************************************************************************
// oaVerilogAnnotate.h
//
// This file contains the definition for the Annotate class. The Annotate
// class is derived from the CallbacksIn class. It is used to annotate existing
// design data with Verilog interface information such as terminal position and 
// bit order.
//
// *****************************************************************************
// Except as specified in the OpenAccess terms of use of Cadence or Silicon
// Integration Initiative, this material may not be copied, modified,
// re-published, uploaded, executed, or distributed in any way, in any medium,
// in whole or in part, without prior written permission from Cadence.
//
//		  Copyright 2003-2005 Cadence Design Systems, Inc.
//			     All Rights	Reserved.
//
//  $Author: shaun $
//  $Revision: 1.14 $
//  $Date: 2005/07/30 07:06:41 $
//  $State: Exp $
// *****************************************************************************
// *****************************************************************************



#ifndef	oaVerilogAnnotate_P
#define	oaVerilogAnnotate_P

BEGIN_VERILOG_NAMESPACE



// *****************************************************************************
// Annotate
// *****************************************************************************
class OA_VERILOG_DLL_API Annotate : public ModuleCallbacksIn {
  public:
			    Annotate(const Scanner  &scannerIn,
				     OptionsIn	    &optionsIn);
    virtual		    ~Annotate();

    void		    init();

  protected:
    virtual void	    all();
    virtual void	    beginModule(const oaString	&name);
    virtual void	    endModule(const ParamList	*ports = NULL,
				       const ParamList	*portParams = NULL);
    virtual void	    moduleInstance(const oaString   &instMasterN,
					   const ParamList  &parameterL,
					   const oaName	    &instNameIn);

    virtual void	    netDeclAssign(const	oaSigTypeEnum	netType,
					  const	oaString	*driveStrOpt,
					  const	oaString	*signedOption,
					  const	Range		*rangeOption,
					  const	ParamList	*delayOption,
					  const	ParamList	&netAssigns);  
    virtual void	    portDeclaration(const oaTermType	termType,
					    const oaSigTypeEnum	netType,
					    const oaString	*signedOpt,
					    const Range		*rangeOpt,
					    const oaName	&portID);

    virtual void	    clearPortOrder(oaModule *module);
};



END_VERILOG_NAMESPACE

#endif