lef53_01.lef.ref

openaccess读def,lef文件所用的源代码

VERSION 5.3 ;
NAMESCASESENSITIVE ON ;
NOWIREEXTENSIONATPIN ON ;
BUSBITCHARS "[]" ;
DIVIDERCHAR ":" ;

PROPERTYDEFINITIONS
  LIBRARY NAME STRING "Cadence96" ;
  LIBRARY librealrangeprop REAL RANGE 21 51 25 ;
  LIBRARY libintrangeprop INTEGER RANGE 20 50 30 ;
  LIBRARY librealprop REAL 21.22 ;
  LIBRARY libintprop INTEGER 20 ;
  LAYER lsp STRING ;
  LAYER lrprange REAL RANGE 1 100 ;
  LAYER liprange INTEGER RANGE 1 100 ;
  LAYER lrp REAL ;
  LAYER lip INTEGER ;
  VIA viasp STRING ;
  VIA viarrangep REAL RANGE 1 100 ;
  VIA COUNT INTEGER RANGE 1 100 ;
  VIA viarp REAL ;
  VIA viaip INTEGER ;
  VIARULE vrsp STRING ;
  VIARULE vrrrp REAL RANGE 1 100 ;
  VIARULE vrirp INTEGER RANGE 1 100 ;
  VIARULE vrrp REAL ;
  VIARULE vrip INTEGER ;
  NONDEFAULTRULE ndrsp STRING ;
  NONDEFAULTRULE ndrfrp REAL RANGE 1 100 ;
  NONDEFAULTRULE ndrirp INTEGER RANGE 1 100 ;
  NONDEFAULTRULE ndrrp REAL ;
  NONDEFAULTRULE ndrip INTEGER ;
  MACRO stringprop STRING ;
  MACRO intrangeprop INTEGER RANGE 1 100 ;
  MACRO WEIGHT REAL RANGE 1 100 ;
  MACRO realprop REAL ;
  MACRO integerprop INTEGER ;
END PROPERTYDEFINITIONS

UNITS
  TIME NANOSECONDS 100 ;
  CAPACITANCE PICOFARADS 10 ;
  DATABASE MICRONS 1000 ;
  FREQUENCY MEGAHERTZ 10 ;
END UNITS
MANUFACTURINGGRID 0.01 ;
USEMINSPACING PIN ON ;
USEMINSPACING OBS OFF ;
CLEARANCEMEASURE MAXXY ;
LAYER DIFF
  TYPE MASTERSLICE ;
  PROPERTY lsp "top" ;
  PROPERTY lrprange 3.5 ;
  PROPERTY liprange 3 ;
  PROPERTY lrp 2 ;
  PROPERTY lip 1 ;
END DIFF

LAYER POLYS
  TYPE MASTERSLICE ;
END POLYS

LAYER CUT01
  TYPE CUT ;
  SPACING 0.2 ;
  ACCURRENTDENSITY PEAK
    FREQUENCY 1e+006 1e+008 ;
    TABLEENTRIES 5e-007 4e-007 ;
  ACCURRENTDENSITY AVERAGE
    FREQUENCY 1e+006 1e+008 ;
    TABLEENTRIES 6e-007 5e-007 ;
  ACCURRENTDENSITY RMS
    FREQUENCY 1e+008 8e+008 ;
    TABLEENTRIES 5e-007 4e-007 ;
  DCCURRENTDENSITY AVERAGE
    CUTAREA 2 5 ;
    TABLEENTRIES 5e-007 4e-007 ;
  PROPERTY lsp "top" ;
  PROPERTY lrprange 3 ;
  PROPERTY liprange 2 ;
  PROPERTY lrp 2.3 ;
  PROPERTY lip 1 ;
END CUT01

LAYER RX
  TYPE ROUTING ;
  DIRECTION HORIZONTAL ;
  PITCH 1.8 ;
  WIDTH 0.05 ;
  AREA 34.1 ;
  SPACING 0.18 ;
  SPACING 0.18 LENGTHTHRESHOLD 1 RANGE 0.3 10.004 ;
  SPACING 0.22 RANGE 0.3 10.004 USELENGTHTHRESHOLD ;
  SPACING 0.6 RANGE 10.005 10000 ;
  SPACING 0.32 RANGE 1.01 1000 INFLUENCE 1.01 ;
  SPACING 0.6 RANGE 4.5 1000 INFLUENCE 3.81 ;
  WIREEXTENSION 0.75 ;
  MINIMUMCUT 2 WIDTH 5 ;
  RESISTANCE RPERSQ 0.103 ;
  CAPACITANCE CPERSQDIST 0.000156 ;
  HEIGHT 9 ;
  THICKNESS 1 ;
  SHRINKAGE 0.1 ;
  CAPMULTIPLIER 1 ;
  EDGECAPACITANCE 5e-005 ;
  ACCURRENTDENSITY PEAK
    FREQUENCY 1e+006 1e+008 ;
    TABLEENTRIES 7e-007 6e-007 ;
  ACCURRENTDENSITY AVERAGE
    FREQUENCY 1e+006 1e+008 ;
    TABLEENTRIES 6e-007 5e-007 ;
  ACCURRENTDENSITY RMS
    FREQUENCY 1e+006 1e+008 ;
    TABLEENTRIES 5e-007 4e-007 ;
  DCCURRENTDENSITY AVERAGE
    WIDTH 20 50 ;
    TABLEENTRIES 6e-007 5e-007 ;
  PROPERTY lrprange 3 ;
  PROPERTY liprange 2 ;
  PROPERTY lrp 2.3 ;
  PROPERTY lip 1 ;
  PROPERTY lsp "top" ;
END RX

LAYER CUT12
  TYPE CUT ;
  SPACING 0.7 LAYER CUT01 ;
  ACCURRENTDENSITY PEAK 5.6e-006 ;
  ACCURRENTDENSITY AVERAGE 5.5e-006 ;
  ACCURRENTDENSITY RMS 5.4e-006 ;
  DCCURRENTDENSITY AVERAGE 4.5e-007 ;
END CUT12

LAYER PC
  TYPE ROUTING ;
  DIRECTION VERTICAL ;
  PITCH 1.8 ;
  WIDTH 1 ;
  MINIMUMCUT 2 WIDTH 5 ;
  ACCURRENTDENSITY PEAK 5.3e-006 ;
  ACCURRENTDENSITY AVERAGE 5.4e-006 ;
  ACCURRENTDENSITY RMS 5.5e-006 ;
  DCCURRENTDENSITY AVERAGE 4.5e-007 ;
END PC

LAYER CA
  TYPE CUT ;
  ACCURRENTDENSITY RMS
    FREQUENCY 1e+008 4e+008 8e+008 ;
    CUTAREA 0.4 0.8 10 50 100 ;
    TABLEENTRIES
       2e-006 1.9e-006 1.8e-006 1.7e-006 1.5e-006
       1.4e-006 1.3e-006 1.2e-006 1.1e-006 1e-006
       9e-007 8e-007 7e-007 6e-007 4e-007 ;
END CA

LAYER M1
  TYPE ROUTING ;
  DIRECTION HORIZONTAL ;
  PITCH 1.8 ;
  WIDTH 1 ;
  ACCURRENTDENSITY RMS
    FREQUENCY 1e+008 4e+008 8e+008 ;
    WIDTH 0.4 0.8 10 50 100 ;
    TABLEENTRIES
       2e-006 1.9e-006 1.8e-006 1.7e-006 1.5e-006
       1.4e-006 1.3e-006 1.2e-006 1.1e-006 1e-006
       9e-007 8e-007 7e-007 6e-007 4e-007 ;
END M1

LAYER V1
  TYPE CUT ;
  SPACING 0.6 LAYER CA ;
END V1

LAYER M2
  TYPE ROUTING ;
  DIRECTION VERTICAL ;
  PITCH 1.8 ;
  WIDTH 0.9 ;
  SPACING 0.9 ;
  WIREEXTENSION 8 ;
  RESISTANCE RPERSQ 0.0608 ;
  CAPACITANCE CPERSQDIST 0.000184 ;
END M2

LAYER V2
  TYPE CUT ;
END V2

LAYER M3
  TYPE ROUTING ;
  DIRECTION HORIZONTAL ;
  PITCH 1.8 ;
  WIDTH 0.9 ;
  SPACING 0.9 ;
  WIREEXTENSION 8 ;
  RESISTANCE RPERSQ 0.0608 ;
  CAPACITANCE CPERSQDIST 0.000184 ;
END M3

LAYER V3
  TYPE CUT ;
END V3

LAYER MT
  TYPE ROUTING ;
  DIRECTION VERTICAL ;
  PITCH 1.8 ;
  WIDTH 0.9 ;
  SPACING 0.9 ;
  RESISTANCE RPERSQ 0.0608 ;
  CAPACITANCE CPERSQDIST 0.000184 ;
END MT

LAYER OVERLAP
  TYPE OVERLAP ;
END OVERLAP

VIA RX_PC DEFAULT
  LAYER RX ;
    RECT -0.7 -0.7 0.7 0.7 ;
  LAYER CUT12 ;
    RECT -0.25 -0.25 0.25 0.25 ;
  LAYER PC ;
    RECT -0.6 -0.6 0.6 0.6 ;
  RESISTANCE 2 ;
  PROPERTY viasp "DEFAULT" ;
  PROPERTY viarrangep 1.99 ;
  PROPERTY COUNT 34 ;
  PROPERTY viarp 1 ;
  PROPERTY viaip 1 ;
END RX_PC

VIA PC_M1 DEFAULT
  LAYER PC ;
    RECT -0.6 -0.6 0.6 0.6 ;
  LAYER CA ;
    RECT -0.25 -0.25 0.25 0.25 ;
  LAYER M1 ;
    RECT -0.6 -0.6 0.6 0.6 ;
  RESISTANCE 1 ;
END PC_M1

VIA M1_M2 DEFAULT
  LAYER M1 ;
    RECT -0.6 -0.6 0.6 0.6 ;
  LAYER V1 ;
    RECT -0.45 -0.45 0.45 0.45 ;
  LAYER M2 ;
    RECT -0.45 -0.45 0.45 0.45 ;
  RESISTANCE 1.5 ;
END M1_M2

VIA M2_M3 DEFAULT
  LAYER M2 ;
    RECT -0.45 -0.9 0.45 0.9 ;
  LAYER V2 ;
    RECT -0.45 -0.45 0.45 0.45 ;
  LAYER M3 ;
    RECT -0.45 -0.45 0.45 0.45 ;
  RESISTANCE 1.5 ;
END M2_M3

VIA M2_M3_PWR
  LAYER M2 ;
    RECT -1.35 -1.35 1.35 1.35 ;
  LAYER V2 ;
    RECT -1.35 -1.35 -0.45 1.35 ;
    RECT 0.45 -1.35 1.35 -0.45 ;
    RECT 0.45 0.45 1.35 1.35 ;
  LAYER M3 ;
    RECT -1.35 -1.35 1.35 1.35 ;
  RESISTANCE 0.4 ;
END M2_M3_PWR

VIA M3_MT DEFAULT
  LAYER M3 ;
    RECT -0.9 -0.45 0.9 0.45 ;
  LAYER V3 ;
    RECT -0.45 -0.45 0.45 0.45 ;
  LAYER MT ;
    RECT -0.45 -0.45 0.45 0.45 ;
  RESISTANCE 1.5 ;
END M3_MT

VIA VIACENTER12
  LAYER M1 ;
    RECT -4.6 -2.2 4.6 2.2 ;
  LAYER V1 ;
    RECT -3.1 -0.8 -1.9 0.8 ;
    RECT 1.9 -0.8 3.1 0.8 ;
  LAYER M2 ;
    RECT -4.4 -2 4.4 2 ;
  RESISTANCE 0.24 ;
END VIACENTER12

VIARULE VIACENTER12_rule
  LAYER M1 ;
    DIRECTION HORIZONTAL ;
    WIDTH 9 TO 9.6 ;
  LAYER M2 ;
    DIRECTION VERTICAL ;
    WIDTH 3 TO 3 ;
  VIA VIACENTER12 ;
END VIACENTER12_rule

VIARULE VIAGEN12 GENERATE
  LAYER M1 ;
    DIRECTION HORIZONTAL ;
    WIDTH 0.1 TO 19 ;
    OVERHANG 1.4 ;
  LAYER M2 ;
    DIRECTION VERTICAL ;
    WIDTH 0.1 TO 19 ;
    OVERHANG 1.4 ;
  LAYER V1 ;
    RECT -0.8 -0.8 0.8 0.8 ;
    SPACING 5.6 BY 6 ;
    RESISTANCE 0.200000 ;
END VIAGEN12

VIARULE VIAGEN12_2 GENERATE
  LAYER M1 ;
    DIRECTION HORIZONTAL ;
  LAYER M2 ;
    DIRECTION VERTICAL ;
  LAYER V1 ;
    RECT -0.8 -0.8 0.8 0.8 ;
    SPACING 5.6 BY 6 ;
END VIAGEN12_2

SPACING
  SAMENET M1 M1 3.5 ;
  SAMENET M2 M2 3.5 ;
  SAMENET CUT01 CA 1.5 ;
  SAMENET CA V1 1.5 STACK ;
  SAMENET V1 V2 1.5 STACK ;
  SAMENET V2 V3 1.5 STACK ;
END SPACING

NONDEFAULTRULE RULE1
  LAYER RX
    WIDTH 10 ;
    SPACING 2.2 ;
    WIREEXTENSION 6 ;
  END RX
  LAYER PC
    WIDTH 10 ;
    SPACING 2.2 ;
  END PC
  LAYER M1
    WIDTH 10 ;
    SPACING 2.2 ;
  END M1
  LAYER M2
    WIDTH 10 ;
    SPACING 2.2 ;
  END M2
  LAYER M3
    WIDTH 11 ;
    SPACING 3.2 ;
  END M3
  LAYER MT
    WIDTH 11 ;
    SPACING 3.2 ;
  END MT
  VIA nd1VIARX0
    LAYER RX ;
      RECT -3 -3 3 3 ;
    LAYER CUT12 ;
      RECT -1 -1 1 1 ;
    LAYER PC ;
      RECT -3 -3 3 3 ;
    RESISTANCE 0.2 ;
    PROPERTY viasp "NONDEFAULT" ;
    PROPERTY viarrangep 1.99 ;
    PROPERTY COUNT 34 ;
    PROPERTY viarp 1 ;
    PROPERTY viaip 1 ;
  END nd1VIARX0

  VIA nd1VIA01
    LAYER PC ;
      RECT -3 -3 3 3 ;
    LAYER CA ;
      RECT -1 -1 1 1 ;
    LAYER M1 ;
      RECT -3 -3 3 3 ;
    RESISTANCE 0.2 ;
  END nd1VIA01

  VIA nd1VIA12
    LAYER M1 ;
      RECT -3 -3 3 3 ;
    LAYER V1 ;
      RECT -1 -1 1 1 ;
    LAYER M2 ;
      RECT -3 -3 3 3 ;
    RESISTANCE 0.2 ;
  END nd1VIA12

  VIA nd1VIA23
    LAYER M2 ;
      RECT -2.2 -2.2 2.2 2.2 ;
    LAYER V2 ;
      RECT -0.8 -0.8 0.8 0.8 ;
    LAYER M3 ;
      RECT -2 -2 2 2 ;
  END nd1VIA23

  VIA nd1VIA34
    LAYER M3 ;
      RECT -2.2 -2.2 2.2 2.2 ;
    LAYER V3 ;
      RECT -0.8 -0.8 0.8 0.8 ;
    LAYER MT ;
      RECT -2 -2 2 2 ;
  END nd1VIA34

  PROPERTY ndrsp "single" ;
  PROPERTY ndrfrp 3.5 ;
  PROPERTY ndrirp 2 ;
  PROPERTY ndrrp 6.7 ;
  PROPERTY ndrip 1 ;
END RULE1
SITE COVER
  CLASS PAD ;
  SIZE 10 BY 10 ;
END COVER

SITE IO
  CLASS PAD ;
  SIZE 80 BY 560 ;
END IO

SITE CORE
  CLASS CORE ;
  SIZE 0.7 BY 8.4 ;
END CORE

SITE CORE1
  CLASS CORE ;
  SYMMETRY X ;
  SIZE 67.2 BY 6 ;
END CORE1

SITE MRCORE
  CLASS CORE ;
  SYMMETRY Y ;
  SIZE 3.6 BY 28.8 ;
END MRCORE

SITE IOWIRED
  CLASS PAD ;
  SIZE 57.6 BY 432 ;
END IOWIRED

SITE IMAGE
  CLASS CORE ;
  SIZE 1 BY 1 ;
END IMAGE

SITE TSTSYM
  CLASS CORE ;
  SYMMETRY X Y R90 ;
  SIZE 3.6 BY 28.8 ;
END TSTSYM

MACRO A
  CLASS CORE ;
  ORIGIN 0 0 ;
  FOREIGN A 0 0 ;
  SIZE 67.2 BY 24 ;
  SYMMETRY X Y R90 ;
  SITE CORE1 ;
  PIN A
    TAPERRULE RULE1 ;
    DIRECTION INPUT ;
    USE SIGNAL ;
    SHAPE ABUTMENT ;
    PORT
      CLASS CORE ;
      LAYER RX ;
        RECT 9 9 80 80 ;
    END
    PORT
      LAYER M1 ;
        RECT 10 10 12 12 ;
        RECT 1 1 2 2 ;
        RECT 1 2 2 3 ;
      LAYER M1 SPACING 5 ;
        RECT 6.6 -0.6 9.6 0.6 ;
        RECT 2 2 10 10 ;
        RECT 2 3 10 11 ;
      LAYER M1 ;
        RECT -0.45 12.15 0.45 13.05 ;
        RECT 2 2 12 12 ;
        RECT 2 3 12 13 ;
      LAYER RX ;
        WIDTH 2 ;
        PATH 10.1 1.5 12.5 1.5 ;
        PATH 5.1 2 9.5 2 ;
        PATH 5.1 3 9.5 3 ;
      LAYER RX SPACING 5 ;
        WIDTH 2 ;
        PATH 15.1 15.5 15.1 3.5 ;
        PATH 15.1 2 19.5 2 ;
        PATH 15.1 3 19.5 3 ;
      LAYER RX ;
        WIDTH 2 ;
        PATH 20.1 20.5 20.1 23.5 ;
        PATH 25.1 2 29.5 2 ;
        PATH 25.1 3 29.5 3 ;
      LAYER PC ;
        RECT 10.2 10.2 15.2 15.2 ;
        RECT 10.2 10.2 15.2 15.2 ;
        RECT 10.2 20.2 15.2 25.2 ;
      LAYER PC SPACING 5 ;
        RECT 10.2 10.2 15.2 15.2 ;
        RECT 10.2 10.2 15.2 15.2 ;
        RECT 10.2 20.2 15.2 25.2 ;
      LAYER PC ;
        RECT 10.2 10.2 15.2 15.2 ;
        RECT 10.2 10.2 15.2 15.2 ;
        RECT 10.2 20.2 15.2 25.2 ;
      VIA 12.2 12.2 RX_PC ;
      VIA 0.5 0.5 PC_M1 ;
      VIA 3.5 0.5 PC_M1 ;
      VIA 0.5 3.5 PC_M1 ;
      VIA 3.5 3.5 PC_M1 ;
    END
  END A
  PIN B
    DIRECTION OUTPUT ;
    USE ANALOG ;
    SHAPE RING ;
  END B
  PIN C
    DIRECTION OUTPUT TRISTATE ;
    USE POWER ;
    SHAPE FEEDTHRU ;
  END C
  PIN D
    DIRECTION INOUT ;
    USE GROUND ;
  END D
  PIN E
    DIRECTION FEEDTHRU ;
    USE CLOCK ;
  END E
  PIN Z
    MUSTJOIN A ;
    DIRECTION INPUT ;
    USE SIGNAL ;
  END Z
  PIN ANTENNASIZEERROR
    DIRECTION OUTPUT ;
    USE SIGNAL ;
  END ANTENNASIZEERROR
  PIN ANTENNAAREAERROR
    DIRECTION OUTPUT ;
    USE SIGNAL ;
  END ANTENNAAREAERROR
  PIN ANTENNALENGTHERROR
    DIRECTION OUTPUT ;
    USE SIGNAL ;
  END ANTENNALENGTHERROR
  PIN ANTENNALENGTHERROR2
    DIRECTION OUTPUT ;
    USE SIGNAL ;
  END ANTENNALENGTHERROR2
  PIN ANTENNALENGTHERROR3
    DIRECTION OUTPUT ;
    USE SIGNAL ;
  END ANTENNALENGTHERROR3
  OBS
    LAYER M1 ;
      RECT 10 10 12 12 ;
      RECT 1 1 2 2 ;
      RECT 1 2 2 3 ;
    LAYER M1 SPACING 5 ;
      RECT 6.6 -0.6 9.6 0.6 ;
      RECT 2 2 10 10 ;
      RECT 2 3 10 11 ;
    LAYER M1 DESIGNRULEWIDTH 0.05 ;
      RECT -0.45 12.15 0.45 13.05 ;
      RECT 2 2 12 12 ;
      RECT 2 3 12 13 ;
    LAYER RX ;
      RECT 9.1 0.5 13.5 2.5 ;
      RECT 4.1 1 10.5 3 ;
      RECT 4.1 2 10.5 4 ;
    LAYER RX SPACING 5 ;
      RECT 14.1 2.5 16.1 16.5 ;
      RECT 14.1 1 20.5 3 ;
      RECT 14.1 2 20.5 4 ;
    LAYER RX DESIGNRULEWIDTH 5 ;
      RECT 19.1 19.5 21.1 24.5 ;
      RECT 24.1 1 30.5 3 ;
      RECT 24.1 2 30.5 4 ;
    LAYER PC ;
      RECT 10.2 10.2 15.2 15.2 ;
      RECT 10.2 10.2 15.2 15.2 ;
      RECT 10.2 20.2 15.2 25.2 ;
    LAYER PC SPACING 5 ;
      RECT 10.2 10.2 15.2 15.2 ;
      RECT 10.2 10.2 15.2 15.2 ;
      RECT 10.2 20.2 15.2 25.2 ;
    LAYER PC DESIGNRULEWIDTH 5 ;
      RECT 10.2 10.2 15.2 15.2 ;
      RECT 10.2 10.2 15.2 15.2 ;
      RECT 10.2 20.2 15.2 25.2 ;
    LAYER RX ;
      RECT 11.5 11.5 12.9 12.9 ;
    LAYER CUT12 ;
      RECT 11.95 11.95 12.45 12.45 ;
    LAYER PC ;
      RECT 11.6 11.6 12.8 12.8 ;
      RECT -0.1 -0.1 1.1 1.1 ;
    LAYER CA ;
      RECT 0.25 0.25 0.75 0.75 ;
    LAYER M1 ;
      RECT -0.1 -0.1 1.1 1.1 ;
    LAYER PC ;
      RECT 2.9 -0.1 4.1 1.1 ;
    LAYER CA ;
      RECT 3.25 0.25 3.75 0.75 ;
    LAYER M1 ;
      RECT 2.9 -0.1 4.1 1.1 ;
    LAYER PC ;
      RECT -0.1 2.9 1.1 4.1 ;
    LAYER CA ;
      RECT 0.25 3.25 0.75 3.75 ;
    LAYER M1 ;
      RECT -0.1 2.9 1.1 4.1 ;
    LAYER PC ;
      RECT 2.9 2.9 4.1 4.1 ;
    LAYER CA ;
      RECT 3.25 3.25 3.75 3.75 ;
    LAYER M1 ;
      RECT 2.9 2.9 4.1 4.1 ;
  END
  PROPERTY stringprop "first" ;
  PROPERTY intrangeprop 2 ;
  PROPERTY WEIGHT 30.31 ;
  PROPERTY realprop 1.1 ;
  PROPERTY integerprop 1 ;
END A

MACRO C
  CLASS CORE ;
  ORIGIN 0 0 ;
  FOREIGN C 0 0 ;
  SIZE 10.8 BY 28.8 ;
  SYMMETRY X Y R90 ;
  SITE CORE ;
END C

MACRO D
  CLASS CORE ;
  ORIGIN 0 0 ;
  FOREIGN D 0 0 ;
  SIZE 67.2 BY 24 ;
END D

MACRO G
  CLASS RING ;
  ORIGIN 0 0 ;
  FOREIGN G 0 0 ;
  SIZE 67.2 BY 24 ;
END G

MACRO H
  CLASS BLOCK ;
  ORIGIN 0 0 ;
  FOREIGN H 0 0 ;
  SIZE 67.2 BY 24 ;
END H

MACRO I
  CLASS COVER ;
  ORIGIN 0 0 ;
  FOREIGN I 0 0 ;
  SIZE 67.2 BY 24 ;
END I

MACRO K
  CLASS PAD ;
  ORIGIN 0 0 ;
  FOREIGN K 0 0 ;
  SIZE 67.2 BY 24 ;
END K

MACRO L
  CLASS PAD ;
  ORIGIN 0 0 ;
  FOREIGN L 0 0 ;
  SIZE 67.2 BY 24 ;
END L

MACRO M
  CLASS PAD ;
  ORIGIN 0 0 ;
  FOREIGN M 0 0 ;
  SIZE 67.2 BY 24 ;
END M

MACRO N
  CLASS PAD ;
  ORIGIN 0 0 ;
  FOREIGN N 0 0 ;
  SIZE 67.2 BY 24 ;
END N

MACRO O
  CLASS PAD ;
  ORIGIN 0 0 ;
  FOREIGN O 0 0 ;
  SIZE 67.2 BY 24 ;
END O

MACRO P
  CLASS CORE ;
  ORIGIN 0 0 ;
  FOREIGN P 0 0 ;
  SIZE 67.2 BY 24 ;
END P

MACRO Q
  CLASS CORE ;
  ORIGIN 0 0 ;
  FOREIGN Q 0 0 ;
  SIZE 67.2 BY 24 ;
END Q

MACRO R
  CLASS ENDCAP TOPLEFT ;
  ORIGIN 0 0 ;
  FOREIGN R 0 0 ;
  SIZE 67.2 BY 24 ;
END R

MACRO S
  CLASS ENDCAP TOPRIGHT ;
  ORIGIN 0 0 ;
  FOREIGN S 0 0 ;
  SIZE 67.2 BY 24 ;
END S

MACRO T
  CLASS ENDCAP BOTTOMLEFT ;
  ORIGIN 0 0 ;
  FOREIGN T 0 0 ;
  SIZE 67.2 BY 24 ;
END T

MACRO U
  CLASS ENDCAP BOTTOMRIGHT ;
  ORIGIN 0 0 ;
  FOREIGN U 0 0 ;
  SIZE 67.2 BY 24 ;
END U

MACRO RECTILINEAR
  CLASS CORE ;
  ORIGIN 0 0 ;
  FOREIGN RECTILINEAR 0 0 ;
  SIZE 1000 BY 1000 ;
  OBS
    LAYER OVERLAP ;
      POLYGON  0 1000  500 1000  500 500  1000 500  1000 0  0 0 ;
  END
END RECTILINEAR

MACRO B
  CLASS CORE ;
  ORIGIN 0 0 ;
  FOREIGN B 0 0 ;
  EEQ A ;
  SIZE 67.2 BY 24 ;
END B

END LIBRARY