lef_overwrite.lef

openaccess读def,lef文件所用的源代码

      RECT -2.2 -2.2 2.2 2.2 ;
    LAYER V2 ;
      RECT -0.8 -0.8 0.8 0.8 ;
    LAYER M3 ;
      RECT -2.0 -2.0 2.0 2.0 ;
  END nd1VIA23
  VIA nd1VIA34
    LAYER M3 ;
      RECT -2.2 -2.2 2.2 2.2 ;
    LAYER V3 ;
      RECT -0.8 -0.8 0.8 0.8 ;
    LAYER MT ;
      RECT -2.0 -2.0 2.0 2.0 ;
  END nd1VIA34
  SPACING
    SAMENET
      CUT01 RX 0.1 STACK ;
  END SPACING
  PROPERTY ndrsp "single" ndrip 1 ndrrp 6.7 ndrirp 2 ndrfrp 3.5 ;
END RULE1

SPACING
  SAMENET CUT01 CA 1.5 ;
  SAMENET CA V1 1.5 STACK ;
  SAMENET M1 M1 3.5 STACK ;
  SAMENET V1 V2 1.5 STACK ;
  SAMENET M2 M2 3.5 STACK ;
  SAMENET V2 V3 1.5 STACK ;
END SPACING


# Crosstalk constructs : obsolete in 5.4; should be ignored.
# ?? Normally it's high low...
UNIVERSALNOISEMARGIN 0.1 20 ;

EDGERATETHRESHOLD1 0.1 ;

EDGERATETHRESHOLD2 0.9 ;

EDGERATESCALEFACTOR 1.0 ;

NOISETABLE 1 ;
  EDGERATE 20 ;
  OUTPUTRESISTANCE 3 ;
  VICTIMLENGTH 25 ;
  VICTIMNOISE 10 ;
END NOISETABLE

CORRECTIONTABLE 1 ;
  EDGERATE 20 ;
  OUTPUTRESISTANCE 3 ;
  VICTIMLENGTH 25 ;
  CORRECTIONFACTOR 10.5 ;
END CORRECTIONTABLE
# end crosstalk

MINFEATURE 0.1 0.1 ;

# dielectric construct : obsolete in 5.4; should be ignored
DIELECTRIC 0.0000345 ;

# irdrop construct : obsolete in 5.4; should be ignored
IRDROP
  TABLE DRESHI
    0.0001 -0.7 0.001 -0.8 0.01 -0.9 0.1 -1.0 ;
  TABLE DRESLO
    0.0001 -1.7 0.001 -1.6 0.01 -1.5 0.1 -1.3 ;
  TABLE DNORESHI
    0.0001 -0.6 0.001 -0.7 0.01 -0.9 0.1 -1.1 ;
  TABLE DNORESLO
    0.0001 -1.5 0.001 -1.5 0.01 -1.4 0.1 -1.4 ;
END IRDROP

SITE COVER
  CLASS PAD ;
  SIZE 10.0 BY 10.0 ;
END  COVER

SITE IO
  CLASS PAD ;
  SIZE 80.0 BY 560.0 ;
END IO

SITE CORE
  CLASS CORE ;
  SIZE 0.7 BY 8.4 ;
END  CORE

SITE CORE1
  CLASS CORE ;
  SYMMETRY X ;
  SIZE 67.2 BY 6 ;
END CORE1

SITE MRCORE
  CLASS CORE ;
  SIZE 3.6 BY 28.8 ;
  SYMMETRY Y ;
END MRCORE

SITE IOWIRED
  CLASS PAD ;
  SIZE 57.6 BY 432 ;
END IOWIRED

SITE IMAGE
  CLASS CORE ;
  SIZE 1 BY 1 ;
END IMAGE

SITE TSTSYM
  CLASS CORE ;
  SIZE 3.6 BY 28.8 ;
  SYMMETRY X Y R90 ;
END TSTSYM

# Array construct : (waiting answer about its obsolescence in 5.4;
# in all cases, not supported by the reader).
ARRAY M7E4XXX
  SITE CORE -5021.450 -4998.000 N DO 14346 BY 595 STEP 0.700 16.800 ;
  SITE CORE -5021.450 -4989.600 FS DO 14346 BY 595 STEP 0.700 16.800 ;
  SITE IO 6148.800 5800.000 E DO 1 BY 1 STEP 0.000 0.000 ;
  SITE IO 6148.800 3240.000 E DO 1 BY 1 STEP 0.000 0.000 ;
  SITE COVER -7315.000 -7315.000 N DO 1 BY 1 STEP 0.000 0.000 ;
  SITE COVER 7305.000 7305.000 N DO 1 BY 1 STEP 0.000 0.000 ;
  CANPLACE COVER -7315.000 -7315.000 N DO 1 BY 1 STEP 0.000 0.000 ;
  CANPLACE COVER -7250.000 -7250.000 N DO 5 BY 1 STEP 40.000 0.000 ;
  CANNOTOCCUPY CORE -5021.450 -4989.600 FS DO 100 BY 595 STEP 0.700 16.800 ;
  CANNOTOCCUPY CORE -5021.450 -4998.000 N DO 100 BY 595 STEP 0.700 16.800 ;
  TRACKS X -6148.800 DO 17569 STEP 0.700 LAYER RX ;
  TRACKS Y -6148.800 DO 20497 STEP 0.600 LAYER RX ;

  FLOORPLAN 100%
    CANPLACE COVER -7315.000 -7315.000 N DO 1 BY 1 STEP 0.000 0.000 ;
    CANPLACE COVER -7250.000 -7250.000 N DO 5 BY 1 STEP 40.000 0.000 ;
    CANPLACE CORE -5021.450 -4998.000 N DO 14346 BY 595 STEP 0.700 16.800 ;
    CANPLACE CORE -5021.450 -4989.600 FS DO 14346 BY 595 STEP 0.700 16.800 ;
    CANNOTOCCUPY CORE -5021.450 -4989.600 FS DO 100 BY 595 STEP 0.700 16.800 ;
    CANNOTOCCUPY CORE -5021.450 -4998.000 N DO 100 BY 595 STEP 0.700 16.800 ;
  END 100%
  GCELLGRID X -6157.200 DO 1467 STEP 8.400 ;
  GCELLGRID Y -6157.200 DO 1467 STEP 8.400 ;

  # Values here-below surely not realistic but just to test the syntax...
  DEFAULTCAP 3
    MINPINS 1 WIRECAP 0.1 ;
    MINPINS 2 WIRECAP 0.2 ;
    MINPINS 3 WIRECAP 0.3 ;
  END DEFAULTCAP
END M7E4XXX
# end array construct

MACRO INV
  CLASS CORE ;
  SOURCE BLOCK ;
  # power should be ignored
  POWER 1.0 ;
  FOREIGN INV 0 0 N ;
  SIZE 67.2 BY 24 ;
  SYMMETRY X Y R90 ;
  SITE CORE1 ;
  PIN Z
    DIRECTION OUTPUT ;
    USE SIGNAL ;
    PORT
      LAYER M1 ;
        WIDTH 1.0 ;
        RECT 0 3 9.9 6 ;
    END
  END Z
  PIN A
    DIRECTION INPUT ;
    USE SIGNAL ;
    PORT
      LAYER M1 ;
        RECT 10 10 12 12 ;
    END
  END A
  OBS
    LAYER RX ;
      WIDTH 2 ;
      PATH 10.1 1.5 12.5 3.5 ;
    LAYER PC SPACING 1.2 ;
      PATH ITERATE 1 1 DO 2 BY 2 STEP 0.5 0.5 ;
    LAYER M1 DESIGNRULEWIDTH 0.8 ;
      RECT 24.1 1.5 43.5 16.5 ;
  END
  # Obsolete timing section in 5.4
  TIMING
    FROMPIN A ;
    TOPIN Z ;
    RISE INTRINSIC .39 .41 1.2 .25 .29 1.8 .67 .87 2.2
      VARIABLE 0.12 0.13 ;
    FALL INTRINSIC .24 .29 1.3 .26 .31 1.7 .6 .8 2.1
      VARIABLE 0.11 0.14 ;
    RISERS 83.178 90.109 ;
    FALLRS 76.246 97.041 ;
    RISECS 0.751 0.751 ;
    FALLCS 0.751 0.751 ;
    RISET0 0.65493 0.65493 ;
    FALLT0 0.38 0.38 ;
    RISESATT1 0 0 ;
    FALLSATT1 0.15 0.15 ;
    UNATENESS INVERT ;
  END TIMING
  # end of obsolete timing section in 5.4
END INV

MACRO INV_B
  SOURCE GENERATE ;
  EEQ INV ;
  LEQ INV ;
  SIZE 67.2 BY 24 ;
  SITE CORE1 ;
  PIN Z
    DIRECTION OUTPUT ;
    USE SIGNAL ;
    PORT
      LAYER M1 ;
        WIDTH 1.0 ;
        RECT 0 3 9.9 6 ;
    END
  END Z
  PIN A
    DIRECTION INPUT ;
    USE SIGNAL ;
    PORT
      LAYER M1 ;
        RECT 10 10 12 12 ;
    END
  END A
  OBS 
    LAYER RX ;
      RECT ITERATE 0.2 0.2 0.4 0.4 DO 2 BY 2 STEP 1 1 ;
    LAYER PC ;
      POLYGON 10.2 10.2 10.2 15.2 15.2 15.2 15.2 10.2 ;
    LAYER M1 ;
      POLYGON ITERATE 5.2 5.2 6 5.2 6 4 5.2 4 DO 2 BY 2 STEP 1 1 ;
  END 
END INV_B

MACRO INV_C
  CLASS RING ;
  SOURCE USER ;
  FOREIGN INV_C ;
  ORIGIN 0.9 0.9 ;
  SIZE 10.8 BY 28.8 ;
  SYMMETRY X Y R90  ;
  SITE CORE ;
  PIN Z
    DIRECTION OUTPUT ;
    USE SIGNAL ;
    PORT
      LAYER M1 ;
        WIDTH 1.0 ;
        RECT 0 3 9.9 6 ;
    END
  END Z
  PIN A
    DIRECTION INPUT ;
    USE SIGNAL ;
    PORT
      LAYER M1 ;
        RECT 10 10 12 12 ;
    END
  END A
  OBS
    LAYER M1 SPACING 5 ;
      RECT 6.6 -0.6 9.6 0.6 ;
      RECT 4.8 12 9.6 13.2 ;
    VIA 12.2 12.2 RX_PC ;
    VIA ITERATE 0.5 0.5 PC_M1 DO 2 BY 2 STEP 3 3 ;
  END
END INV_C


# All MACRO PIN syntax covered in CHK3A macro
MACRO CHK3A
  SIZE 100 BY 100 ;
  PIN GND
    FOREIGN GROUND STRUCTURE 0 0 E ;
    LEQ A ;
    DIRECTION INOUT ;
    USE GROUND ;
    SHAPE ABUTMENT ;
    # follow 19 attributes should be ignored
    INPUTNOISEMARGIN  6.1 2.3 ;
    OUTPUTNOISEMARGIN 5.0 4.6 ;
    OUTPUTRESISTANCE 7.4 5.4 ;
    POWER 2.0 ;
    LEAKAGE 1.0 ;
    CAPACITANCE 0.1 ;
    RESISTANCE 0.2 ;
    PULLDOWNRES 0.5 ;
    TIEOFFR 0.8 ;
    VHI 5 ;
    VLO 0 ;
    RISEVOLTAGETHRESHOLD 2.0 ;
    FALLVOLTAGETHRESHOLD 2.0 ;
    RISETHRESH 22 ;
    FALLTHRESH 100 ;
    RISESATCUR 4 ;
    FALLSATCUR .5 ;
    CURRENTSOURCE ACTIVE ;
    IV_TABLES LOWT HIGHT ;
    # end of attributes to ignore
    PROPERTY strprop "special" intprop 23 realprop 24.25 intrangeprop 2 realrangeprop 3.4 ;
    PORT
      CLASS CORE ;
      LAYER M1 SPACING 0.05 ;
        WIDTH 1.0 ;
        RECT -0.9 3 9.9 6 ;
      VIA 100 300 M1_M2 ;
    END
  END GND
  PIN VDD
    DIRECTION INOUT ;
    USE POWER ;
    SHAPE ABUTMENT ;
    PORT
      CLASS NONE ;
      LAYER M1 ;
        RECT ITERATE -0.9 21 9.9 24 DO 1 BY 2 STEP 1 1 ;
      VIA ITERATE 100 300 M1_M2 DO 1 BY 2 STEP 1 2 ;
    END
  END VDD
  PIN PA3
    DIRECTION INPUT ;
    # 5.4
    ANTENNAPARTIALMETALAREA 4 LAYER M1 ;
    ANTENNAPARTIALMETALAREA 2 ;
    ANTENNAPARTIALMETALSIDEAREA 5 LAYER M1 ;
    ANTENNAPARTIALMETALSIDEAREA 5 ;
    ANTENNAGATEAREA 2 ;
    ANTENNAGATEAREA 3 LAYER M1 ;
    ANTENNADIFFAREA 1 LAYER M1 ;
    ANTENNADIFFAREA 1 ;
    ANTENNAMAXAREACAR 1 LAYER M1 ;
    ANTENNAMAXSIDEAREACAR 1 LAYER M1 ;
    ANTENNAPARTIALCUTAREA 1 ;
    ANTENNAPARTIALCUTAREA 2 LAYER M1 ;
    ANTENNAMAXCUTCAR 1 LAYER M1 ;
    PORT
      LAYER M1 SPACING 0.02 ;
        RECT 1.35 -0.45 2.25 0.45 ;
	RECT -0.45 -0.45 0.45 0.45 ;
    END
    PORT
      LAYER PC DESIGNRULEWIDTH 0.05 ;
        RECT -0.45 12.15 0.45 13.05 ;
    END
    PORT
      LAYER PC ;
        RECT -0.45 24.75 0.45 25.65 ;
    END
  END PA3
  PIN PA0
    FOREIGN MYFOREIGNPIN ;
    DIRECTION INPUT ;
    MUSTJOIN PA3 ;
    PORT
      LAYER M1 ;
	 RECT 8.55 8.55 9.45 9.45 ;
	 RECT 6.75 6.75 7.65 7.65 ;
      END
    PORT
      LAYER PC ;
	 RECT 8.55 24.75 9.45 25.65 ;
      END
  END PA0
  PIN PA2
    DIRECTION FEEDTHRU ;
    USE CLOCK ;
    SHAPE FEEDTHRU ;
    PORT
      LAYER M1 ;
	 POLYGON 15 35 15 60 65 60 65 35 ;
    END
    PORT
      LAYER M1 ;
        PATH 8.55 12.15 9.45 13.05 ;
    END
  END PA2
  PIN PA10
    DIRECTION OUTPUT ;
    USE SIGNAL ;
    PORT
      LAYER M1 ;
	POLYGON ITERATE 20 35 20 60 70 60 70 35 DO 1 BY 2 STEP 5 5 ;
    END
    PORT
      LAYER M1 ;
	PATH ITERATE 5.55 12.15 10.45 13.05 DO 1 BY 2 STEP 2 2 ;
    END
  END PA10
  PIN PA1
    DIRECTION OUTPUT TRISTATE ;
    USE ANALOG ;
    SHAPE RING ;
    PORT
      LAYER M1 ;
	RECT 8.55 -0.45 9.45 0.45 ;
	RECT 6.75 -0.45 7.65 0.45 ;
    END
  END PA1
  PIN NODIR
    PORT
      LAYER M1 ;
        RECT 6.75 -0.45 7.65 0.45 ;
    END
  END NODIR
  PROPERTY stringprop "first" integerprop 1 realprop 1.1 WEIGHT 30.31 intrangeprop 2 ;
END CHK3A

MACRO BADSITESYNTAX
  CLASS CORE SPACER ;
  SIZE 18 BY 28.8 ;
  ORIGIN 0.9 0.9 ;
  # SITE syntax not supported by my reader
  SITE CORE 34 54 FE DO 30 BY 3 STEP 1 1 ;
  PIN I1
    DIRECTION INPUT ;
    PORT
      LAYER M1 ;
        WIDTH 1.0 ;
        RECT 0 3 9.9 6 ;
    END
  END I1
  PIN O1
    DIRECTION OUTPUT ;
    PORT
      LAYER M1 ;
        RECT 10 10 12 12 ;
    END
  END O1
END BADSITESYNTAX

MACRO RECTILINEAR
  SIZE 1000 BY 1000 ;
  PIN Z 
    DIRECTION OUTPUT ;
    PORT 
      LAYER M1 ;
        WIDTH 1.0 ;
        RECT 0 3 9.9 6 ;
    END
  END Z
  PIN A 
    DIRECTION INPUT ;
    PORT
      LAYER M1 ;
        RECT 10 10 12 12 ;
    END
  END A
  OBS 
    LAYER OVERLAP ;
      RECT 0 0 500 1000 ;
      RECT 500 0 1000 500 ;
  END 
END RECTILINEAR

BEGINEXT "SIGNATURE"
  CREATOR "CADENCE"
  DATE "09/27/01"
ENDEXT

END LIBRARY
#------------------------------------------------------------------------------