lef55_01.lef

openaccess读def,lef文件所用的源代码

  END RX
  LAYER PC
    WIDTH 10.1 ;
    SPACING 2.2 ;
  END PC
  LAYER M1
    WIDTH 10.1 ;
    SPACING 2.2 ;
  END M1
  LAYER M2
    WIDTH 10.1 ;
    SPACING 2.2 ;
  END M2
  LAYER M3
    WIDTH 11.1 ;
    SPACING 3.2 ;
  END M3
  LAYER  MT
    WIDTH 11.1 ;
    SPACING 3.2 ;
  END MT
  VIA nd1VIARX0
    RESISTANCE 0.2 ;
    LAYER RX ;
      RECT -3 -3 3 3 ;
    LAYER CUT12 ;
      RECT -1.1 -1.1 1.1 1.1 ;
    LAYER PC ;
      RECT -3 -3 3 3 ;
    PROPERTY viasp "NONDEFAULT" viaip 1 viarp 1.1 COUNT 34 viarrangep 1.99 ;
  END nd1VIARX0
  VIA nd1VIA01
    RESISTANCE 0.2 ;
    LAYER PC ;
      RECT -3 -3 3 3 ;
    LAYER CA ;
      RECT -1.1 -1.1 1.1 1.1 ;
    LAYER M1 ;
      RECT -3 -3 3 3 ;
  END nd1VIA01
  VIA nd1VIA12
    FOREIGN IN1X 0.1 0.1 N ;
    RESISTANCE 0.2 ;
    LAYER M1 ;
      RECT -3 -3 3 3 ;
    LAYER V1 ;
      RECT -1.1 -1.1 1.1 1.1 ;
    LAYER M2 ;
      RECT -3 -3 3 3 ;
  END nd1VIA12
  VIA nd1VIA23
    LAYER M2 ;
      RECT -2.2 -2.2 2.2 2.2 ;
    LAYER V2 ;
      RECT -0.8 -0.8 0.8 0.8 ;
    LAYER M3 ;
      RECT -2.1 -2.1 2.1 2.1 ;
  END nd1VIA23
  VIA nd1VIA34
    LAYER M3 ;
      RECT -2.2 -2.2 2.2 2.2 ;
    LAYER V3 ;
      RECT -0.8 -0.8 0.8 0.8 ;
    LAYER MT ;
      RECT -2.1 -2.1 2.1 2.1 ;
  END nd1VIA34
  SPACING
    SAMENET
      CUT01 RX 0.1 STACK ;
  END SPACING
  PROPERTY ndrsp "single" ndrip 1 ndrrp 6.7 ndrirp 2 ndrfrp 3.5 ;
END RULE1

SPACING
  SAMENET CUT01 CA 1.5 ;
  SAMENET CA V1 1.5 STACK ;
  SAMENET M1 M1 3.5 STACK ;
  SAMENET V1 V2 1.5 STACK ;
  SAMENET M2 M2 3.5 STACK ;
  SAMENET V2 V3 1.5 STACK ;
END SPACING


# Crosstalk constructs : obsolete in 5.4; should be ignored.
# ?? Normally it's high low...
UNIVERSALNOISEMARGIN 0.1 20 ;

EDGERATETHRESHOLD1 0.1 ;

EDGERATETHRESHOLD2 0.9 ;

EDGERATESCALEFACTOR 1.1 ;

NOISETABLE 1 ;
  EDGERATE 20 ;
  OUTPUTRESISTANCE 3 ;
  VICTIMLENGTH 25 ;
  VICTIMNOISE 10 ;
END NOISETABLE

CORRECTIONTABLE 1 ;
  EDGERATE 20 ;
  OUTPUTRESISTANCE 3 ;
  VICTIMLENGTH 25 ;
  CORRECTIONFACTOR 10.5 ;
END CORRECTIONTABLE
# end crosstalk

MINFEATURE 0.1 0.1 ;

# dielectric construct : obsolete in 5.4; should be ignored
DIELECTRIC 0.0000345 ;

# irdrop construct : obsolete in 5.4; should be ignored
IRDROP
  TABLE DRESHI
    0.0001 -0.7 0.001 -0.8 0.01 -0.9 0.1 -1.1 ;
  TABLE DRESLO
    0.0001 -1.7 0.001 -1.6 0.01 -1.5 0.1 -1.3 ;
  TABLE DNORESHI
    0.0001 -0.6 0.001 -0.7 0.01 -0.9 0.1 -1.1 ;
  TABLE DNORESLO
    0.0001 -1.5 0.001 -1.5 0.01 -1.4 0.1 -1.4 ;
END IRDROP

SITE COVER
  CLASS PAD ;
  SIZE 10.1 BY 10.1 ;
END  COVER

SITE IO
  CLASS PAD ;
  SIZE 80.1 BY 560.1 ;
END IO

SITE CORE
  CLASS CORE ;
  SIZE 0.7 BY 8.4 ;
END  CORE

SITE CORE1
  CLASS CORE ;
  SYMMETRY X ;
  SIZE 67.2 BY 6 ;
END CORE1

SITE MRCORE
  CLASS CORE ;
  SYMMETRY Y ;
  SIZE 3.6 BY 28.8 ;
END MRCORE

SITE IOWIRED
  CLASS PAD ;
  SIZE 57.6 BY 432 ;
END IOWIRED

SITE IMAGE
  CLASS CORE ;
  SIZE 1 BY 1 ;
END IMAGE

SITE TSTSYM
  CLASS CORE ;
  SYMMETRY X Y R90 ;
  SIZE 3.6 BY 28.8 ;
END TSTSYM

# Array construct : (waiting answer about its obsolescence in 5.4;
# in all cases, not supported by the reader).
ARRAY M7E4XXX
  SITE CORE -5021.450 -4998.000 N DO 14346 BY 595 STEP 0.700 16.800 ;
  SITE CORE -5021.450 -4989.600 FS DO 14346 BY 595 STEP 0.700 16.800 ;
  SITE IO 6148.800 5800.000 E DO 1 BY 1 STEP 0.000 0.000 ;
  SITE IO 6148.800 3240.000 E DO 1 BY 1 STEP 0.000 0.000 ;
  SITE COVER -7315.000 -7315.000 N DO 1 BY 1 STEP 0.000 0.000 ;
  SITE COVER 7305.000 7305.000 N DO 1 BY 1 STEP 0.000 0.000 ;
  CANPLACE COVER -7315.000 -7315.000 N DO 1 BY 1 STEP 0.000 0.000 ;
  CANPLACE COVER -7250.000 -7250.000 N DO 5 BY 1 STEP 40.000 0.000 ;
  CANNOTOCCUPY CORE -5021.450 -4989.600 FS DO 100 BY 595 STEP 0.700 16.800 ;
  CANNOTOCCUPY CORE -5021.450 -4998.000 N DO 100 BY 595 STEP 0.700 16.800 ;
  TRACKS X -6148.800 DO 17569 STEP 0.700 LAYER RX ;
  TRACKS Y -6148.800 DO 20497 STEP 0.600 LAYER RX ;

  FLOORPLAN 100%
    CANPLACE COVER -7315.000 -7315.000 N DO 1 BY 1 STEP 0.000 0.000 ;
    CANPLACE COVER -7250.000 -7250.000 N DO 5 BY 1 STEP 40.000 0.000 ;
    CANPLACE CORE -5021.450 -4998.000 N DO 14346 BY 595 STEP 0.700 16.800 ;
    CANPLACE CORE -5021.450 -4989.600 FS DO 14346 BY 595 STEP 0.700 16.800 ;
    CANNOTOCCUPY CORE -5021.450 -4989.600 FS DO 100 BY 595 STEP 0.700 16.800 ;
    CANNOTOCCUPY CORE -5021.450 -4998.000 N DO 100 BY 595 STEP 0.700 16.800 ;
  END 100%
  GCELLGRID X -6157.200 DO 1467 STEP 8.400 ;
  GCELLGRID Y -6157.200 DO 1467 STEP 8.400 ;

  # Values here-below surely not realistic but just to test the syntax...
  DEFAULTCAP 3
    MINPINS 1 WIRECAP 0.1 ;
    MINPINS 2 WIRECAP 0.2 ;
    MINPINS 3 WIRECAP 0.3 ;
  END DEFAULTCAP
END M7E4XXX
# end array construct

MACRO A
  CLASS CORE ;
  SOURCE USER ;
  POWER 1.1 ; # Obsolete: power should be ignored
  FOREIGN A 1 1 N ;
  SIZE 67.2 BY 24 ;
  SYMMETRY X Y R90 ;
  SITE CORE1 ;

  PIN A
    TAPERRULE RULE1 ;
    FOREIGN AFOREIGNPIN STRUCTURE 1 1 S ;
    DIRECTION INPUT ;
    USE SIGNAL ;
    SHAPE ABUTMENT ;

    ANTENNAPARTIALMETALAREA 16.2 LAYER M2 ;
    ANTENNAPARTIALMETALSIDEAREA 18.2 LAYER M2 ;
    ANTENNAPARTIALCUTAREA       26.2 LAYER M2 ;
    ANTENNADIFFAREA             22.2 LAYER RX ;

    ANTENNAMODEL OXIDE1 ;		# LEF5.5
    ANTENNAGATEAREA             20.2 LAYER M2 ;
    ANTENNAMAXAREACAR          20.2 LAYER POLYS ;
    ANTENNAMAXSIDEAREACAR      30.2 LAYER M2 ;
    ANTENNAMAXCUTCAR           50.2 LAYER V2 ;

    ANTENNAMODEL OXIDE2 ;		# LEF5.5
    ANTENNAGATEAREA             21.2 LAYER POLYS ;
    ANTENNAMAXAREACAR          21.2 LAYER M2 ;
    ANTENNAMAXSIDEAREACAR      31.2 LAYER M2 ;
    ANTENNAMAXCUTCAR           51.2 LAYER V2 ;

    PORT
      CLASS NONE ;
      LAYER M1 ;
        RECT 10 10 12 12 ;
	RECT ITERATE 1 1 2 2 DO 1 BY 2 STEP 1 1 ;
      LAYER M1 SPACING 5 ;
        RECT 6.6 -0.6 9.6 0.6 ;
	RECT ITERATE 10 10 2 2 DO 1 BY 2 STEP 1 1 ;
      LAYER M1 DESIGNRULEWIDTH 0.05 ;
        RECT -0.45 12.15 0.45 13.05 ;
	RECT ITERATE 12 12 2 2 DO 1 BY 2 STEP 1 1 ;
      LAYER RX ;
        WIDTH 2 ;
        PATH 10.1 1.5 12.5 1.5 ;
        PATH ITERATE 5.1 2 9.5 2 DO 1 BY 2 STEP 1 1 ;
      LAYER RX SPACING 5 ;
        WIDTH 2 ;
        PATH 15.1 15.5 15.1 3.5 ;
        PATH ITERATE 15.1 2 19.5 2 DO 1 BY 2 STEP 1 1 ;
      LAYER RX DESIGNRULEWIDTH 5 ;
        WIDTH 2 ;
        PATH 20.1 20.5 20.1 23.5 ;
        PATH ITERATE 25.1 2 29.5 2 DO 1 BY 2 STEP 1 1 ;
      LAYER PC ;
        POLYGON 10.2 10.2 10.2 15.2 15.2 15.2 15.2 10.2 ;
        POLYGON ITERATE 10.2 10.2 10.2 15.2 15.2 15.2 15.2 10.2
          DO 1 BY 2 STEP 10 10 ;
      LAYER PC SPACING 5 ;
        POLYGON 10.2 10.2 10.2 15.2 15.2 15.2 15.2 10.2 ;
        POLYGON ITERATE 10.2 10.2 10.2 15.2 15.2 15.2 15.2 10.2
          DO 1 BY 2 STEP 10 10 ;
      LAYER PC DESIGNRULEWIDTH 5 ;
        POLYGON 10.2 10.2 10.2 15.2 15.2 15.2 15.2 10.2 ;
        POLYGON ITERATE 10.2 10.2 10.2 15.2 15.2 15.2 15.2 10.2
          DO 1 BY 2 STEP 10 10 ;
      VIA 12.2 12.2 RX_PC ;
      VIA ITERATE 0.5 0.5 PC_M1 DO 2 BY 2 STEP 3 3 ;
    END

    PORT
      CLASS CORE ;
      LAYER RX ;
        RECT 9 9 80 80 ;
    END

    # follow 19 attributes should be ignored
    INPUTNOISEMARGIN  6.1 2.3 ;
    OUTPUTNOISEMARGIN 5.1 4.6 ;
    OUTPUTRESISTANCE 7.4 5.4 ;
    POWER 2.1 ;
    LEAKAGE 1.1 ;
    CAPACITANCE 0.1 ;
    RESISTANCE 0.2 ;
    PULLDOWNRES 0.5 ;
    TIEOFFR 0.8 ;
    VHI 5 ;
    VLO 0 ;
    RISEVOLTAGETHRESHOLD 2.1 ;
    FALLVOLTAGETHRESHOLD 2.1 ;
    RISETHRESH 22 ;
    FALLTHRESH 100 ;
    RISESATCUR 4 ;
    FALLSATCUR .5 ;
    CURRENTSOURCE ACTIVE ;
    IV_TABLES LOWT HIGHT ;
    # end of attributes to ignore
  END A

  PIN B
    LEQ A ;
    FOREIGN AFOREIGNPINB STRUCTURE 2 2 ;
    DIRECTION OUTPUT ;
    USE ANALOG ;
    SHAPE RING ;

    ANTENNAPARTIALMETALAREA 16.2 ;
    ANTENNAPARTIALMETALSIDEAREA 18.2 ;
    ANTENNAPARTIALCUTAREA       26.2 ;
    ANTENNADIFFAREA             22.2 ;

    ANTENNAMODEL OXIDE1 ;		# LEF5.5
    ANTENNAGATEAREA             20.2 ;

    ANTENNAMODEL OXIDE2 ;		# LEF5.5
    ANTENNAGATEAREA             21.2 ;

  END B

  PIN C
    FOREIGN AFOREIGNPINC STRUCTURE ;
    DIRECTION OUTPUT TRISTATE ;
    USE POWER ;
    SHAPE FEEDTHRU ;
 
    # Old 5.4 antenna syntax (no antennamodel)
    ANTENNAPARTIALMETALAREA 3.2 LAYER M1 ;
    ANTENNAPARTIALMETALAREA 4.2 LAYER M2 ;
    ANTENNAPARTIALMETALSIDEAREA 5.2 LAYER M1 ;
    ANTENNAPARTIALMETALSIDEAREA 6.2 LAYER M2 ;
    ANTENNAPARTIALCUTAREA      13.2 LAYER V1 ;
    ANTENNAPARTIALCUTAREA      14.2 LAYER V2 ;
    ANTENNADIFFAREA             9.2 LAYER M1 ;
    ANTENNADIFFAREA            10.2 LAYER M2 ;
    ANTENNAGATEAREA             7.2 LAYER M1 ;
    ANTENNAGATEAREA             8.2 LAYER M2 ;
    ANTENNAMAXAREACAR          20.2 LAYER M2 ;
    ANTENNAMAXSIDEAREACAR      30.2 LAYER M2 ;
    ANTENNAMAXCUTCAR           50.2 LAYER V2 ;
  END C

  PIN D
    FOREIGN AFOREIGNPIND ;
    DIRECTION INOUT ;
    USE GROUND ;
  END D

  PIN E
    FOREIGN AFOREIGNPIN STRUCTURE ;
    DIRECTION FEEDTHRU ;
    USE CLOCK ;
  END E

  PIN Z
    DIRECTION INPUT ;
    USE SIGNAL ;
    SHAPE ABUTMENT ;
    MUSTJOIN A ;
  END Z

  OBS
    LAYER M1 ;
      RECT 10 10 12 12 ;
      RECT ITERATE 1 1 2 2 DO 1 BY 2 STEP 1 1 ;
    LAYER M1 SPACING 5 ;
      RECT 6.6 -0.6 9.6 0.6 ;
      RECT ITERATE 10 10 2 2 DO 1 BY 2 STEP 1 1 ;
    LAYER M1 DESIGNRULEWIDTH 0.05 ;
      RECT -0.45 12.15 0.45 13.05 ;
      RECT ITERATE 12 12 2 2 DO 1 BY 2 STEP 1 1 ;
    LAYER RX ;
      WIDTH 2 ;
      PATH 10.1 1.5 12.5 1.5 ;
      PATH ITERATE 5.1 2 9.5 2 DO 1 BY 2 STEP 1 1 ;
    LAYER RX SPACING 5 ;
      WIDTH 2 ;
      PATH 15.1 15.5 15.1 3.5 ;
      PATH ITERATE 15.1 2 19.5 2 DO 1 BY 2 STEP 1 1 ;
    LAYER RX DESIGNRULEWIDTH 5 ;
      WIDTH 2 ;
      PATH 20.1 20.5 20.1 23.5 ;
      PATH ITERATE 25.1 2 29.5 2 DO 1 BY 2 STEP 1 1 ;
    LAYER PC ;
      POLYGON 10.2 10.2 10.2 15.2 15.2 15.2 15.2 10.2 ;
      POLYGON ITERATE 10.2 10.2 10.2 15.2 15.2 15.2 15.2 10.2
        DO 1 BY 2 STEP 10 10 ;
    LAYER PC SPACING 5 ;
      POLYGON 10.2 10.2 10.2 15.2 15.2 15.2 15.2 10.2 ;
      POLYGON ITERATE 10.2 10.2 10.2 15.2 15.2 15.2 15.2 10.2
        DO 1 BY 2 STEP 10 10 ;
    LAYER PC DESIGNRULEWIDTH 5 ;
      POLYGON 10.2 10.2 10.2 15.2 15.2 15.2 15.2 10.2 ;
      POLYGON ITERATE 10.2 10.2 10.2 15.2 15.2 15.2 15.2 10.2
        DO 1 BY 2 STEP 10 10 ;
    VIA 12.2 12.2 RX_PC ;
    VIA ITERATE 0.5 0.5 PC_M1 DO 2 BY 2 STEP 3 3 ;
    LAYER OVERLAP ;
      RECT 0 0 20 10 ;
  END
  
  # Obsolete timing section since 5.4
  TIMING 
    FROMPIN A ;
    TOPIN Z ;
    RISE INTRINSIC .39 .41 1.2 .25 .29 1.8 .67 .87 2.2
      VARIABLE 0.12 0.13 ;
    FALL INTRINSIC .24 .29 1.3 .26 .31 1.7 .6 .8 2.1
      VARIABLE 0.11 0.14 ;
    RISERS 83.178 90.109 ;
    FALLRS 76.246 97.041 ;
    RISECS 0.751 0.751 ;
    FALLCS 0.751 0.751 ;
    RISET0 0.65493 0.65493 ;
    FALLT0 0.38 0.38 ;
    RISESATT1 0 0 ;
    FALLSATT1 0.15 0.15 ;
    UNATENESS INVERT ;
  END TIMING
  # end of obsolete timing section in 5.4

  PROPERTY stringprop "first" integerprop 1 realprop 1.1 WEIGHT 30.31 intrangeprop 2 ;
END A

MACRO B
  CLASS CORE FEEDTHRU ;
  SOURCE BLOCK ;
  SYMMETRY X ;
  FOREIGN C 10 10 N ;
  FOREIGN D 20 20 N ;
  EEQ A ;
  LEQ A ;
  SIZE 67.2 BY 24 ;
END B

MACRO C
  CLASS CORE TIEHIGH ;
  SYMMETRY Y ;
  FOREIGN C -0.9 -0.9 ;
  ORIGIN 0.9 0.9 ;
  SIZE 10.8 BY 28.8 ;
  SITE CORE 34 54 FE DO 30 BY 3 STEP 1 1 ;
END C

MACRO D
  CLASS CORE TIELOW ;
  SYMMETRY X Y ;
  SIZE 67.2 BY 24 ;
END D

MACRO E
  CLASS CORE SPACER ;
  SIZE 67.2 BY 24 ;
END E

MACRO F
  CLASS CORE ANTENNACELL ;
  SIZE 67.2 BY 24 ;
END F

MACRO G
  CLASS RING ;
  SIZE 67.2 BY 24 ;
END G

MACRO H
  CLASS BLOCK ;
  SIZE 67.2 BY 24 ;
END H

MACRO I
  CLASS COVER ;
  SIZE 67.2 BY 24 ;
END I

MACRO J
  CLASS COVER BUMP ;
  SIZE 67.2 BY 24 ;
END J

MACRO K
  CLASS PAD INPUT ;
  SIZE 67.2 BY 24 ;
END K

MACRO L
  CLASS PAD OUTPUT ;
  SIZE 67.2 BY 24 ;
END L

MACRO M
  CLASS PAD INOUT ;
  SIZE 67.2 BY 24 ;
END M

MACRO N
  CLASS PAD POWER ;
  SIZE 67.2 BY 24 ;
END N

MACRO O
  CLASS PAD SPACER ;
  SIZE 67.2 BY 24 ;
END O

MACRO P
  CLASS ENDCAP PRE ;
  SIZE 67.2 BY 24 ;
END P

MACRO Q
  CLASS ENDCAP POST ;
  SIZE 67.2 BY 24 ;
END Q

MACRO R
  CLASS ENDCAP TOPLEFT ;
  SIZE 67.2 BY 24 ;
END R

MACRO S
  CLASS ENDCAP TOPRIGHT ;
  SIZE 67.2 BY 24 ;
END S

MACRO T
  CLASS ENDCAP BOTTOMLEFT ;
  SIZE 67.2 BY 24 ;
END T

MACRO U
  CLASS ENDCAP BOTTOMRIGHT ;
  SIZE 67.2 BY 24 ;
END U

MACRO V
  CLASS BLOCK BLACKBOX ;
  SIZE 67.2 BY 24 ;
END V

MACRO W
  CLASS PAD AREAIO ;
  SIZE 67.2 BY 24 ;
END W

MACRO RECTILINEAR
  SIZE 1000 BY 1000 ;
  OBS
    LAYER OVERLAP ;
      RECT 0 0 500 1000 ;
      RECT 500 0 1000 500 ;
  END
END RECTILINEAR

BEGINEXT "SIGNATURE"
  CREATOR "CADENCE"
  DATE "09/27/01"
ENDEXT

END LIBRARY
#------------------------------------------------------------------------------