bios.c

利用DSP/BIOS在CCS2.2下开发的通过EMIF读取SRAM中数据的工程

#include"BIOScfg.h"
#include"CAChead.h"
#include<csl.h>
#include<csl_emif.h>
#include<csl_gpio.h>
#include <c55.h>

int16   *SRAM0_addr=(int16 *)0x100000;//CEn0
int16   *SRAM1_addr=(int16 *)0x200000;//CEn1
int16   *startn=(int16 *)0x400000;//CEn2
int16   *DSP_rereqn=(int16 *)0x600000;//CEn3
int16   slot_allot[PORT_NUM];
REQ_MEM req_memory;
DIS_MEM dis_memory;

void test();
int CACPdistribute(int16 slot_allot[PORT_NUM]);
int CACUdistribute(REQ_PORT requestion,DIS_PORT distribution,int port_slot);


void main(){
  GPIO_pinEnable(GPIO_PIN1);
  GPIO_pinDirection(GPIO_PIN1,GPIO_OUTPUT);
  GPIO_pinWrite(GPIO_PIN1,1);
     
  if(CACPdistribute(slot_allot)){
    LOG_printf(&trace,"The resource is alloted !\n");
  }
  LOG_printf(&trace,"main over !\n");
  
  C55_enableIER0(0x0008);
  *startn=1;
  return;                     
}


void Init_fun(){
  EMIF_Config EMIF_SRAM={//CE0 and CE1 is set to SRAM mode
                         //MYTYPE is 16bit SRAM
                         //RDSETUP RDSTROBE RDHOLD RDEXGLD are all 2
                         //WRSETUP WRSTROBE WRHOLD WREXGLD are all 2 
                         0x0008, /*EGCR*/
                         0xFFFF, /* emirst */
                         0x1211, /* ce01 */ //setup2 strobe4 hold1
                         0xA211, /* ce02 */ //rdexhld2 wrexhld2 setup2 strobe4 hold1
                         0x00FF, /* ce03 */
                         0x1211, /* ce11 */
                         0xA211, /* ce12 */
                         0x00FF, /* ce13 */
                         0x1211, /* ce21 */
                         0xA201, /* ce22 */
                         0x00FF, /* ce23 */
                         0x1211, /* ce31 */
                         0xA211, /* ce32 */
                         0x00FF, /* ce33 */
                         0x07FF, /* sdc1 */
                         0x0FFF, /* sdper */
                         0x07FF, /* init */
                         0x03FF /* sdc2 */};
  EMIF_config(&EMIF_SRAM);   

}

int CACPdistribute(int16 slot_allot[PORT_NUM]){
  int i;
  for(i=0;i<PORT_NUM;i++){
    slot_allot[i]=SLOT_NUM_PER_PORT-USER_NUM_PER_PORT*PROTECT_SLOT;
  }
  return success;
}

void test(){
  
  int16 u=0;
  int16 result;
  int16 check;
  int16 port;
  int16 *req_addr=SRAM0_addr;
  int16 *dis_addr=SRAM1_addr;
  
  port=*req_addr++;
  for(u=0;u<USER_NUM_PER_PORT;u++){
    req_memory[port][u].port_id=*req_addr++;
    req_memory[port][u].user_id=*req_addr++;
    req_memory[port][u].slot_num=*req_addr++;
    req_memory[port][u].p=*req_addr++;
    req_memory[port][u].t=*req_addr++;
  }
  check=*req_addr;
  GPIO_pinWrite(GPIO_PIN1,0);
  GPIO_pinWrite(GPIO_PIN1,1);
  while(GPIO_pinRead(GPIO_PIN1)==0);
  if(check==2048){
    result=CACUdistribute(req_memory[port],dis_memory[port],slot_allot[port]);  
    if(result==success){
      *dis_addr++=port;
      for(u=0;u<USER_NUM_PER_PORT;u++){
        *dis_addr++=dis_memory[port][u].port_id;
        *dis_addr++=dis_memory[port][u].user_id;
         *dis_addr++=dis_memory[port][u].req_slot;
        *dis_addr++=dis_memory[port][u].start_slot;
        *dis_addr++=dis_memory[port][u].end_slot;
      }
      *dis_addr++=2048;
      *DSP_rereqn=0;
    }
    else if(result==failure){
      LOG_printf(&trace,"No resource !\n");
    } 
    else{
      LOG_printf(&trace,"No request !\n");
    }    
  }
  else
    LOG_printf(&trace,"Reading failed !\n");

  LOG_printf(&trace,"test over !\n");
  //*startn=1;
  return;  
}
int CACUdistribute(REQ_PORT requestion,DIS_PORT distribution,int port_slot){
  int i=0;
  int user=0;
  int end=0;
  int reqslot[USER_NUM_PER_PORT];
  int disslot[USER_NUM_PER_PORT];
  int average;
  int finish;
  int remain_slot;
  
  if(port_slot==0){
    return failure;
  }
  
  for(i=0,user=0;i<USER_NUM_PER_PORT;i++){
     reqslot[i]=requestion[i].slot_num;
     disslot[i]=0;
     if(reqslot[i]){
     user++;
     }
  }
  
  if(user==0){
    return nonereq;
  }
  else{
    remain_slot=port_slot;
    finish=0;
    while(user!=0 && finish==0){
         finish=1;
         average=remain_slot/user;
         for(i=0;i<USER_NUM_PER_PORT;i++){
            if(disslot[i]<reqslot[i] && reqslot[i]<average){
              disslot[i]=reqslot[i];
              remain_slot=remain_slot-disslot[i];
              user--;
              finish=0;
            }
            else if(disslot[i]<reqslot[i]){
              disslot[i]=average;
            }
            else{
              disslot[i]=reqslot[i];
            }
         }
    }     
  }
  for(i=0,end=0;i<USER_NUM_PER_PORT;i++){
     if(reqslot[i]){
       distribution[i].port_id=requestion[i].port_id;
       distribution[i].user_id=requestion[i].user_id;
       distribution[i].req_slot=requestion[i].slot_num;
       distribution[i].start_slot=end;
       distribution[i].end_slot=end+disslot[i]-1;
       end=distribution[i].end_slot+1+PROTECT_SLOT;
     }
     else{
       distribution[i].port_id=requestion[i].port_id;
       distribution[i].user_id=requestion[i].user_id;
       distribution[i].req_slot=0;
       distribution[i].start_slot=null;
       distribution[i].end_slot=null;
     }
     
  }
  return success;
}