autosale.vhd

VHDL编写的自动售货机

--
--  File: D:\fndtn\active\projects\aaasas\autosale.vhd
-- created: 09/23/04 10:28:30
--  from: 'D:\fndtn\active\projects\aaasas\autosale.asf'
--  by fsm2hdl - version: 2.0.1.60
--
library IEEE;
use IEEE.std_logic_1164.all;

use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;

library SYNOPSYS;
use SYNOPSYS.attributes.all;

entity autosale is 
  port (C: in STD_LOGIC;
        CLK: in STD_LOGIC;
        E: in STD_LOGIC;
        M: in STD_LOGIC;
        RD: in STD_LOGIC;
        SK: in STD_LOGIC;
        SS: in STD_LOGIC;
        BD: out STD_LOGIC;
        IND: out STD_LOGIC;
        KD: out STD_LOGIC;
        Q2: out STD_LOGIC_VECTOR (3 downto 0);
        SD: out STD_LOGIC;
        Q1: inout STD_LOGIC_VECTOR (3 downto 0));
end;

architecture autosale_arch of autosale is

-- diagram signals declarations
signal Y: STD_LOGIC;

-- SYMBOLIC ENCODED state machine: Sreg0
type Sreg0_type is (S1, S2, S3, S4);
signal Sreg0: Sreg0_type;

begin
-- concurrent signals assignments


Sreg0_machine: process (CLK, rd)

begin

if RD='0' then
	Q1<="0000";
	Q2<="0000";
	IND<='0';
	BD<='0';
	KD<='0';
	SD<='0';
	Y<=SK xor SS;
	Sreg0 <= S1;
elsif CLK'event and CLK = '1' then
	case Sreg0 is
		when S1 =>
			Q1<="0000";
			Q2<="0000";
			IND<='0';
			BD<='0';
			KD<='0';
			SD<='0';
			Y<=SK xor SS;
			if Y='1' then
				Sreg0 <= S2;
			elsif Y='0' then
				Sreg0 <= S1;
			end if;
		when S2 =>
			IND<='1';
			BD<='0';
			Q2<="0000";
			SD<='0';
			KD<='0';
			if C='1' or Y='0' then
				Sreg0 <= S1;
			elsif M='0' then
				Sreg0 <= S2;
			elsif M='1' then
				Sreg0 <= S3;
				Q1<=Q1+1;
			end if;
		when S3 =>
			Y<=SK xor SS;
			if E='1' and C='0' and Q1>="0011" and Y='1' then
				Sreg0 <= S4;
				KD<=SK;
				SD<=SS;
				Q1<=Q1-3;
			elsif E='1' and Q1<"0011" and Y='1' then
				Sreg0 <= S4;
			elsif C='1' and Y='1' then
				Sreg0 <= S4;
			elsif Y='0' then
				Sreg0 <= S3;
			elsif M='1' then
				Sreg0 <= S3;
				Q1<=Q1+1;
			elsif M='0' then
				Sreg0 <= S3;
				Q1<=Q1;
			end if;
		when S4 =>
			BD<='1';
			IND<='0';
			Q2<=Q1;
			Y<=SK xor SS;
			if C='1' or Y='0' then
				Sreg0 <= S1;
			elsif Y='1' then
				Sreg0 <= S2;
				Q1<="0000";
			end if;
		when others =>
			null;
	end case;
end if;
end process;

end autosale_arch;