map_7263.h

ST72T63游戏杆源程序

/**************** (c) 1998       STMicroelectronics **********************

PROJECT : 
COMPILER : ST7 HICROSS C (HIWARE)

MODULE  :  map_7263.h
VERSION :  V 1.0

CREATION DATE :  25/05/98

AUTHOR : / MICROCONTROLLER DIVISION / ST Rousset

-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-

DESCRIPTION : ST72E63 Hardware Register Mapping.

                                  This file contains the description of the hardware register of
                                  the ST72E63 IC. Variable forced to a fixed address.

                                  WARNING : this file need a specific LINKER configuration file !

-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-

MODIFICATIONS :


******************************************************************************/

#ifndef MAP_7263_H
#define MAP_7263_H

#include <hidef.h>

/* A PORT REGISTERS */
#pragma DATA_SEG SHORT ST7_PA
extern volatile Byte PADR;                                      /* PORT A : Data                                                */
extern          Byte PADDR;                                      /*                      Data Direction          */

/* B PORT REGISTERS */
#pragma DATA_SEG SHORT ST7_PB
extern volatile Byte PBDR;                                      /* PORT B : Data                                                */
extern         Byte PBDDR;                                      /*                      Data Direction          */
                        
/* C PORT REGISTERS */
#pragma DATA_SEG SHORT ST7_PC
extern volatile Byte PCDR;                                      /* PORT C : Data                                                */
extern         Byte PCDDR;                                      /*                      Data Direction          */

/* **********************
        MISCELLANEOUS REGISTER *****************************************************
        ********************** */

#pragma DATA_SEG SHORT ST7_MISCR
extern volatile Byte MISCR;                                      /* Miscellaneous Register               */


/* ****************************
        ALTERNATE FUNCTION REGISTERS ***********************************************
        **************************** */

/* A/D CONVERTER */
#pragma DATA_SEG SHORT ST7_ADC
extern volatile Byte ADCDR;                                     /* Data Register                                                */
extern volatile Byte ADCCSR;                            /* Control/Status Register              */

// WATCHDOG
#pragma DATA_SEG SHORT ST7_WDG
extern volatile Byte WDGCR;                                     // Watchdog Control Register            
        
/* EXTERNAL INTERRUPTS */
#pragma DATA_SEG SHORT ST7_INT
extern volatile Byte ITRFRE;               /* External Interrupt Managnt   */        

/* TIMER (TIM5) */
#pragma DATA_SEG SHORT ST7_TIM
extern volatile Byte TIMCR2;                            /* Control Register 2                           */
extern volatile Byte TIMCR1;                            /* Control Register 1                           */
extern volatile Byte TIMSR;                                     /* Status Register                                      */
extern volatile Byte TIMICHR1;                          /* Input  Capture 1 High Reg            */
extern volatile Byte TIMICLR1;                          /* Input  Capture 1 Low  Reg            */
extern volatile Byte TIMOCHR1;                          /* Output Compare 1 High Reg            */
extern volatile Byte TIMOCLR1;                          /* Output Compare 1 Low  Reg            */
extern volatile Byte TIMCHR;                            /* Counter High Register                        */
extern volatile Byte TIMCLR;                            /* Counter Low  Register                        */
extern volatile Byte TIMACHR;                           /* Alternate Counter High Reg   */
extern volatile Byte TIMACLR;                           /* Alternate Counter Low       Reg      */
extern volatile Byte TIMICHR2;                          /* Input  Capture 2 High Reg            */
extern volatile Byte TIMICLR2;                          /* Input  Capture 2 Low  Reg            */
extern volatile Byte TIMOCHR2;                          /* Output Compare 2 High Reg            */
extern volatile Byte TIMOCLR2;                          /* Output Compare 2 Low  Reg            */

/* SCI */
#pragma DATA_SEG SHORT ST7_SCI
extern volatile Byte SCISR;                                     /* Status Register                                      */
extern volatile Byte SCIDR;                                     /* Data Register(Read & Write)  */
extern volatile Byte SCIBRR;                            /* Baud Rate Register                           */
extern volatile Byte SCICR1;                            /* Control Register 1                           */
extern volatile Byte SCICR2;                            /* Control Register 2                           */

// USB 
#pragma DATA_SEG SHORT ST7_USB
extern volatile Byte USBPIDR;                           // PID Register
extern volatile Byte USBDMAR;                           // DMA Address Register
extern volatile Byte USBIDR;                            // Interrupt/DMA Register
extern volatile Byte USBISTR;                           // Interrupt Status Register
extern volatile Byte USBIMR;                            // Interrupt Mask Register
extern volatile Byte USBCTLR;                           // Control Register
extern volatile Byte USBDADDR;                          // Device Address Register
extern volatile Byte USBEP0RA;                          // Endpoint0 Register A (Tx)
extern volatile Byte USBEP0RB;                          // Endpoint0 Register B (Rx)
extern volatile Byte USBEP1RA;                          // Endpoint1 Register A (Tx)
extern volatile Byte USBEP1RB;                          // Endpoint1 Register B (Rx)
extern volatile Byte USBEP2RA;                          // Endpoint2 Register A (Tx)
extern volatile Byte USBEP2RB;                          // Endpoint2 Register B (Rx)

/* I2C INTERFACE */
#pragma DATA_SEG SHORT ST7_I2C
extern volatile Byte I2CDR;                                     /* Data Register                                                */
                Byte I2creserved;                        /* RESERVED                                                     */
extern          Byte I2COAR;                             /* (7bit) Slave address Register */
extern          Byte I2CCCR;                             /* Clock Control Register                       */
extern volatile Byte I2CSR2;                            /* Status Register 2                            */
extern volatile Byte I2CSR1;                            /* Status Register 1                            */
extern volatile Byte I2CCR;                                     /* Control Register                                     */


#pragma DATA_SEG DEFAULT

#endif
/*** (c) 1998   STMicroelectronics ****************** END OF FILE ***/