map_7263.c

ST72T63游戏杆源程序

/**************** (c) 1998       STMicroelectronics **********************

PROJECT : 
COMPILER : ST7 HICROSS C (HIWARE)

MODULE  :  map_7263.c
VERSION :  V 1.1

CREATION DATE :  25/05/98

AUTHOR : / MICROCONTROLLER DIVISION / ST Rousset

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DESCRIPTION : ST72E63 Hardware Register Mapping.

                                  This file contains the description of the hardware register of
                                  the ST72E63 IC. Variable forced to a fixed address.

                                  WARNING : this file need a specific LINKER configuration file !

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MODIFICATIONS :
Rev 1.1 23/09/98
-Added:
#include "map_7263.h"

******************************************************************************/

#include <hidef.h>
#include "map_7263.h"

/* A PORT REGISTERS */
#pragma DATA_SEG SHORT ST7_PA
volatile Byte PADR;                                      /* PORT A : Data                                                */
         Byte PADDR;                                      /*                      Data Direction          */

/* B PORT REGISTERS */
#pragma DATA_SEG SHORT ST7_PB
volatile Byte PBDR;                                      /* PORT B : Data                                                */
        Byte PBDDR;                                      /*                      Data Direction          */
                        
/* C PORT REGISTERS */
#pragma DATA_SEG SHORT ST7_PC
volatile Byte PCDR;                                      /* PORT C : Data                                                */
        Byte PCDDR;                                      /*                      Data Direction          */

/* **********************
        MISCELLANEOUS REGISTER *****************************************************
        ********************** */

#pragma DATA_SEG SHORT ST7_MISCR
volatile Byte MISCR;                                      /* Miscellaneous Register               */


/* ****************************
        ALTERNATE FUNCTION REGISTERS ***********************************************
        **************************** */

/* A/D CONVERTER */
#pragma DATA_SEG SHORT ST7_ADC
volatile Byte ADCDR;                                     /* Data Register                                                */
volatile Byte ADCCSR;                            /* Control/Status Register              */

// WATCHDOG
#pragma DATA_SEG SHORT ST7_WDG
volatile Byte WDGCR;                                     // Watchdog Control Register            
        
/* EXTERNAL INTERRUPTS */
#pragma DATA_SEG SHORT ST7_INT
volatile Byte ITRFRE;               /* External Interrupt Managnt   */        

/* TIMER (TIM5) */
#pragma DATA_SEG SHORT ST7_TIM
volatile Byte TIMCR2;                            /* Control Register 2                           */
volatile Byte TIMCR1;                            /* Control Register 1                           */
volatile Byte TIMSR;                                     /* Status Register                                      */
volatile Byte TIMICHR1;                          /* Input  Capture 1 High Reg            */
volatile Byte TIMICLR1;                          /* Input  Capture 1 Low  Reg            */
volatile Byte TIMOCHR1;                          /* Output Compare 1 High Reg            */
volatile Byte TIMOCLR1;                          /* Output Compare 1 Low  Reg            */
volatile Byte TIMCHR;                            /* Counter High Register                        */
volatile Byte TIMCLR;                            /* Counter Low  Register                        */
volatile Byte TIMACHR;                           /* Alternate Counter High Reg   */
volatile Byte TIMACLR;                           /* Alternate Counter Low       Reg      */
volatile Byte TIMICHR2;                          /* Input  Capture 2 High Reg            */
volatile Byte TIMICLR2;                          /* Input  Capture 2 Low  Reg            */
volatile Byte TIMOCHR2;                          /* Output Compare 2 High Reg            */
volatile Byte TIMOCLR2;                          /* Output Compare 2 Low  Reg            */

/* SCI */
#pragma DATA_SEG SHORT ST7_SCI
volatile Byte SCISR;                                     /* Status Register                                      */
volatile Byte SCIDR;                                     /* Data Register(Read & Write)  */
volatile Byte SCIBRR;                            /* Baud Rate Register                           */
volatile Byte SCICR1;                            /* Control Register 1                           */
volatile Byte SCICR2;                            /* Control Register 2                           */

// USB 
#pragma DATA_SEG SHORT ST7_USB
volatile Byte USBPIDR;                           // PID Register
volatile Byte USBDMAR;                           // DMA Address Register
volatile Byte USBIDR;                            // Interrupt/DMA Register
volatile Byte USBISTR;                           // Interrupt Status Register
volatile Byte USBIMR;                            // Interrupt Mask Register
volatile Byte USBCTLR;                           // Control Register
volatile Byte USBDADDR;                          // Device Address Register
volatile Byte USBEP0RA;                          // Endpoint0 Register A (Tx)
volatile Byte USBEP0RB;                          // Endpoint0 Register B (Rx)
volatile Byte USBEP1RA;                          // Endpoint1 Register A (Tx)
volatile Byte USBEP1RB;                          // Endpoint1 Register B (Rx)
volatile Byte USBEP2RA;                          // Endpoint2 Register A (Tx)
volatile Byte USBEP2RB;                          // Endpoint2 Register B (Rx)

/* I2C INTERFACE */
#pragma DATA_SEG SHORT ST7_I2C
volatile Byte I2CDR;                                     /* Data Register                                                */
         Byte I2creserved;                        /* RESERVED                                                     */
         Byte I2COAR;                             /* (7bit) Slave address Register */
         Byte I2CCCR;                             /* Clock Control Register                       */
volatile Byte I2CSR2;                            /* Status Register 2                            */
volatile Byte I2CSR1;                            /* Status Register 1                            */
volatile Byte I2CCR;                                     /* Control Register                                     */

/*** (c) 1998   STMicroelectronics ****************** END OF FILE ***/