📄 dac.lst
字号:
MCS-51 MACRO ASSEMBLER SA_ADC_TEST 06/30/95 PAGE 1
DOS 5.0 (038-N) MCS-51 MACRO ASSEMBLER, V2.3
OBJECT MODULE PLACED IN DAC.OBJ
ASSEMBLER INVOKED BY: C:\LANG\ASM51\ASM51.EXE DAC.ASM
LOC OBJ LINE SOURCE
1 NAME SA_ADC_Test
2
3 ; Test program to loop on Successive Approximation A-to-D conversion.
4 ; Allows digital codes and resulting DAC output to be viewed on 'scope.
5
6
---- 7 DSEG AT 0020H
8
0060 9 ORG 0060H ; stack origin
0060 10 stack: DS 0020H ; stack depth
11
12
---- 13 CSEG
14
0000 15 ORG 0000H ; power on/reset vector
0000 020080 16 jmp on_reset
17
0003 18 ORG 0003H ; external interrupt 0 vector
0003 32 19 reti ; undefined
20
000B 21 ORG 000BH ; timer 0 overflow vector
000B 32 22 reti ; undefined
23
0013 24 ORG 0013H ; external interrupt 1 vector
0013 32 25 reti ; undefined
26
001B 27 ORG 001BH ; timer 1 overflow vector
001B 32 28 reti ; undefined
29
0023 30 ORG 0023H ; serial I/O interrupt vector
0023 32 31 reti ; undefined
32
0040 33 ORG 0040H ; begin constant data space
34
0080 35 ORG 0080H ; begin code space
36 USING 0 ; register bank zero
37 on_reset:
0080 75815F 38 mov sp, #(stack-1) ; initialize stack pointer
39
0083 75A800 40 mov IE, #0 ; deactivate all interrupts
0086 74FF 41 mov a, #0ffh ; deactivate output ports
0088 F590 42 mov p1, a ;
008A F5B0 43 mov p3, a ;
44
45 loop:
008C 120091 46 call ADC ; convert
008F 80FB 47 sjmp loop ; again
48
49
50 ADC:
MCS-51 MACRO ASSEMBLER SA_ADC_TEST 06/30/95 PAGE 2
LOC OBJ LINE SOURCE
51
52 ; Convert analog-to-digital.
53 ; Executes a successive approximation algorithm in an attempt to
54 ; find an eight-bit code which causes the DAC output to match the
55 ; unknown voltage at the comparator input. The algorithm returns
56 ; one of 256 values ranging from 00000000 (zero volts) to 11111111
57 ; (full scale). The exact correspondence between the code and input
58 ; voltage is determined in hardware.
59 ; Before the search begins, zeros are written to the DAC and the
60 ; comparator is checked to verify that its output is low. If it is
61 ; not, a code of zero is returned immediately. If the routine
62 ; completes and the comparator output has never gone high, a code
63 ; of all ones is returned, corresponding to full scale.
64 ; Delays have been inserted to allow for worst case op amp slew rate,
65 ; resulting in a conversion time of approximately 275 microseconds.
66 ; The code is returned in A. All other registers are preserved.
67
0091 C0F0 68 push b ; save
0093 8FF0 69 mov b, r7 ;
0095 C0F0 70 push b ;
71
0097 75F000 72 mov b, #0 ; first code
009A 1200C3 73 call DAC ; write DAC
74
009D 00 75 nop ; wait for op amp to slew F.S. to zero
009E 00 76 nop ; plus settling time
009F 00 77 nop ; total five uS at 12 MHz
00A0 00 78 nop ;
00A1 00 79 nop ;
80
00A2 20B615 81 jb p3.6, xxx ; exit if comparator high
82
00A5 C3 83 clr c ; intialize loop counter/bit mask
00A6 7480 84 mov a, #10000000b ;
85 aaa:
00A8 42F0 86 orl b, a ; set bit in DAC code
00AA 1200C3 87 call DAC ; try new code
88
00AD 00 89 nop ; wait for op amp to slew 1/2 F.S.
00AE 00 90 nop ; plus settling time
00AF 00 91 nop ; total five uS at 12 MHz
00B0 00 92 nop ;
00B1 00 93 nop ;
94
00B2 30B602 95 jnb p3.6, bbb ; jump if voltage still low, keep bit
00B5 62F0 96 xrl b, a ; voltage too high, reset bit
97 bbb:
00B7 13 98 rrc a ; shift loop counter/bit mask
00B8 50EE 99 jnc aaa ; loop until bit in mask moves into C
100 xxx:
00BA E5F0 101 mov a, b ; return code in A
102
00BC D0F0 103 pop b ; restore
00BE AFF0 104 mov r7, b ;
00C0 D0F0 105 pop b ;
MCS-51 MACRO ASSEMBLER SA_ADC_TEST 06/30/95 PAGE 3
LOC OBJ LINE SOURCE
00C2 22 106 ret
107
108
109 DAC:
110
111 ; Write the eight bit code in register B to the DAC.
112 ; The six most significant bits of the code are written to the
113 ; six most significant bits of port one. The two least significant
114 ; bits of the code are written to bits five and four of port three.
115 ; It is assumed that the comparator is in use, so the bits in port
116 ; one corresponding to the comparator inputs are set.
117 ; All unused bits are undisturbed.
118 ; No delays are included for DAC settling or op amp slewing.
119 ; All registers are preserved.
120
00C3 C0F0 121 push b ; save code
00C5 43F003 122 orl b, #00000011b ; enable comparator
00C8 85F090 123 mov p1, b ; write bits seven to two
00CB D0F0 124 pop b ; restore code
00CD A2F1 125 mov c, b.1 ; write bit one
00CF 92B5 126 mov p3.5, c ;
00D1 A2F0 127 mov c, b.0 ; write bit zero
00D3 92B4 128 mov p3.4, c ;
00D5 22 129 ret
130
131
132 END
MCS-51 MACRO ASSEMBLER SA_ADC_TEST 06/30/95 PAGE 4
SYMBOL TABLE LISTING
------ ----- -------
N A M E T Y P E V A L U E A T T R I B U T E S
AAA . . . . C ADDR 00A8H A
ADC . . . . C ADDR 0091H A
B . . . . . D ADDR 00F0H A
BBB . . . . C ADDR 00B7H A
DAC . . . . C ADDR 00C3H A
IE. . . . . D ADDR 00A8H A
LOOP. . . . C ADDR 008CH A
ON_RESET. . C ADDR 0080H A
P1. . . . . D ADDR 0090H A
P3. . . . . D ADDR 00B0H A
SA_ADC_TEST ---- ----
SP. . . . . D ADDR 0081H A
STACK . . . D ADDR 0060H A
XXX . . . . C ADDR 00BAH A
REGISTER BANK(S) USED: 0
ASSEMBLY COMPLETE, NO ERRORS FOUND
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -