📄 slmg.mdl
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Model {
Name "slmg1"
Version 2.20
SimParamPage Solver
SampleTimeColors off
InvariantConstants off
WideVectorLines off
ShowLineWidths off
StartTime "0.0"
StopTime "1200"
Solver ode45
RelTol "1e-3"
AbsTol "1e-3"
Refine "1"
MaxStep "0.1"
InitialStep "auto"
FixedStep "auto"
MaxOrder 5
OutputOption RefineOutputTimes
OutputTimes "[]"
LoadExternalInput off
ExternalInput "[t, u]"
SaveTime off
TimeSaveName "tout"
SaveState off
StateSaveName "xout"
SaveOutput off
OutputSaveName "yout"
LoadInitialState off
InitialState "xInitial"
SaveFinalState off
FinalStateName "xFinal"
LimitMaxRows off
MaxRows "1000"
Decimation "1"
AlgebraicLoopMsg warning
MinStepSizeMsg warning
UnconnectedInputMsg warning
UnconnectedOutputMsg warning
UnconnectedLineMsg warning
ConsistencyChecking off
ZeroCross on
SimulationMode normal
RTWSystemTargetFile "grt.tlc"
RTWInlineParameters off
RTWPlaceOutputsASAP off
RTWRetainRTWFile off
RTWTemplateMakefile "grt_default_tmf"
RTWMakeCommand "make_rtw"
RTWGenerateCodeOnly off
ExtModeMexFile "ext_comm"
ExtModeBatchMode off
BlockDefaults {
Orientation right
ForegroundColor black
BackgroundColor white
DropShadow off
NamePlacement normal
FontName "Helvetica"
FontSize 10
FontWeight normal
FontAngle normal
ShowName on
}
AnnotationDefaults {
HorizontalAlignment center
VerticalAlignment middle
ForegroundColor black
BackgroundColor white
DropShadow off
FontName "Helvetica"
FontSize 10
FontWeight normal
FontAngle normal
}
LineDefaults {
FontName "Helvetica"
FontSize 9
FontWeight normal
FontAngle normal
}
System {
Name "slmg1"
Location [286, 84, 786, 384]
Open on
ToolBar on
StatusBar on
ScreenColor white
PaperOrientation landscape
PaperPositionMode auto
PaperType usletter
PaperUnits inches
Block {
BlockType Clock
Name "Clock"
Position [335, 25, 355, 45]
Location [12, 31, 119, 76]
}
Block {
BlockType Fcn
Name "Fcn"
Position [85, 80, 120, 110]
Expr "-0.1*u[1]+0.2*u[2]/(1+power(u[2],10))"
}
Block {
BlockType Integrator
Name "Integrator"
Ports [1, 1, 0, 0, 0]
Position [205, 85, 225, 105]
ExternalReset none
InitialConditionSource internal
InitialCondition "1.2"
LimitOutput off
UpperSaturationLimit "inf"
LowerSaturationLimit "-inf"
ShowSaturationPort off
ShowStatePort off
AbsoluteTolerance "auto"
}
Block {
BlockType Mux
Name "Mux"
Ports [2, 1, 0, 0, 0]
Position [70, 171, 105, 229]
Orientation left
Inputs "2"
}
Block {
BlockType TransportDelay
Name "Transport\nDelay"
Position [195, 200, 235, 230]
Orientation left
DelayTime "17"
InitialInput "0"
BufferSize "1024"
}
Block {
BlockType Reference
Name "XY Graph"
Ports [2, 0, 0, 0, 0]
Position [420, 72, 450, 103]
SourceBlock "simulink/Sinks/XY Graph"
SourceType "XY scope."
xmin "0"
xmax "1200"
ymin "0.2"
ymax "1.4"
st "-1"
}
Block {
BlockType ZeroOrderHold
Name "Zero-Order\nHold"
Position [295, 79, 330, 111]
SampleTime "1"
}
Line {
SrcBlock "Fcn"
SrcPort 1
DstBlock "Integrator"
DstPort 1
}
Line {
SrcBlock "Transport\nDelay"
SrcPort 1
DstBlock "Mux"
DstPort 2
}
Line {
SrcBlock "Mux"
SrcPort 1
Points [-20, 0; 0, -105]
DstBlock "Fcn"
DstPort 1
}
Line {
SrcBlock "Integrator"
SrcPort 1
Points [0, 0]
Branch {
DstBlock "Zero-Order\nHold"
DstPort 1
}
Branch {
Points [25, 0; 0, 90]
Branch {
Points [0, 30]
DstBlock "Transport\nDelay"
DstPort 1
}
Branch {
DstBlock "Mux"
DstPort 1
}
}
}
Line {
SrcBlock "Zero-Order\nHold"
SrcPort 1
DstBlock "XY Graph"
DstPort 2
}
Line {
SrcBlock "Clock"
SrcPort 1
Points [25, 0; 0, 45]
DstBlock "XY Graph"
DstPort 1
}
Annotation {
Position [252, 77]
VerticalAlignment top
Text "x(t)"
}
Annotation {
Position [152, 217]
VerticalAlignment top
Text "x(t-tau)"
}
Annotation {
Position [152, 167]
VerticalAlignment top
Text "x(t) "
}
Annotation {
Position [102, 62]
VerticalAlignment top
Text "-0.1x(t)+x(t-tau)/[1+x(t-tau)^10]"
}
}
}
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