dcisr.c

此為philip 1362 USB DOS下的驅動程式包, 已經共測試並內含有說明文件

/*
   //*************************************************************************
   //
   //                  P H I L I P S   P R O P R I E T A R Y
   //
   //           COPYRIGHT (c)   2000-2002 BY PHILIPS SINGAPORE.
   //                     --  ALL RIGHTS RESERVED  --
   //
   // File Name:	DcISR.C
   // Created:		Feb. 1, 2000
   // Modified:		May 30, 2002
   // Revision:		1.0
   //
   //*************************************************************************
   //
   //*************************************************************************
   // Implementation Notes,
   //   ISR hierachy
   //
*/
#include <stdio.h>
#include <string.h>
#include <dos.h>
#include <conio.h>

#include "SysCnfg.h"

#include "BasicTyp.h"
#include "DcCommon.h"

#include "HAL4Sys.h"
#include "HAL4ISA.h"
#include "HAL4IKit.h"

#include "HAL4D13.h"
#include "D13_Reg.h"
#include "D13_DcS.h"

#include "USB100.h"

#include "DcISR.h"
#include "DcHandle.h"

#include "Hal4Otg.h"
#include "OtgSvc.h"
#include "HCISR.h"

/*
//*************************************************************************
//  Public static data
//*************************************************************************
*/
extern	UCHAR			bIRQL;
extern  UCHAR			bVerbose;
// Task Control Block
extern DC_TCB			D13TaskControlBlock;

// USB Device Info
extern USB_DEV_INFO		D13_DevInfo;

// USB Default Control Pipe
extern CONTROL_XFER		DCPCtrlXfer;
extern OTG_TCB 			OtgTcb;
extern UCHAR 			IRQ4D13_CHNNL;

/*
//*************************************************************************
//  Private static data
//*************************************************************************
*/

void interrupt (*OldISR_D13)();


/*
//*************************************************************************
//  ISR Subroutine
//*************************************************************************
*/

void interrupt ISR_4D13(void)
{
	ULONG 	dwDCIntSource;
	USHORT	wHCIntSource;
	USHORT	wOTGIntSource;
	UCHAR	byReentryCounter = MAX_ISRREENTRY_NUM;

	dwDCIntSource = D13_ReadInterruptRegister();
	if(dwDCIntSource & ~0x00000080)	//DC interrupt
	{
		do {
			byReentryCounter -- ;
			if( FALSE == ISR_IntSrcSnoopy(dwDCIntSource))
				break;
			else
				dwDCIntSource = D13_ReadInterruptRegister();
		}while(byReentryCounter != 0);
	}
	else	//HC or OTG interrupt
	{
		fn_SHC_isr();
	}

	if (IRQ4D13_CHNNL >= 8)
	{
		Hal4Sys_OutportB(0xA0, 0x20); //PIC-1 cascading to PIC-1
		Hal4Sys_OutportB(0x20, 0x20); //PIC-0
	}
	else
	{
		Hal4Sys_OutportB(0x20, 0x20); //PIC-0
	}

/*	do {

		byReentryCounter -- ;
		if( FALSE == ISR_IntSrcSnoopy())
			break;
	}while(byReentryCounter != 0);*/

//	if( 0 == byReentryCounter)
//		cprintf("Fatal Error: CPU is too slow to handle Irq\n!");
}

BOOLEAN ISR_IntSrcSnoopy(ULONG dwIrqSource)
{
//	ULONG   dwIrqSource;
	BOOLEAN IsAnyInt = TRUE;

	bIRQL = 1;

//	dwIrqSource = D13_ReadInterruptRegister();
//	if(dwIrqSource != 0x08)
//		printf("Interrupt: DC!\n");
	if( dwIrqSource & D13REG_INTSRC_BUSRESET)
	{
		ISR_BusReset();
	}
	if( dwIrqSource & D13REG_INTSRC_RESUME)
	{
		ISR_BusResume();
	}
	else if(dwIrqSource & D13REG_INTSRC_SUSPEND)
	{
		ISR_SuspendChange();
	}
	else if(dwIrqSource & D13REG_INTSRC_EOT)
	{
		ISR_DmaEot();
	}
	else if(dwIrqSource & (D13REG_INTSRC_SOF))
	{
		ISR_SOF();
	}
	else if(dwIrqSource & (D13REG_INTSRC_PSEUDO_SOF))
	{
		ISR_PseudoSOF();
	}
	else
	{
		if(dwIrqSource & D13REG_INTSRC_EP0IN)
			ISR_Ep00TxDone();
		if(dwIrqSource & D13REG_INTSRC_EP0OUT)
			ISR_Ep00RxDone();
		if(dwIrqSource & D13REG_INTSRC_EP01)
			ISR_Ep01Done();
		if(dwIrqSource & D13REG_INTSRC_EP02)
			ISR_Ep02Done();
		if(dwIrqSource & D13REG_INTSRC_EP03)
			ISR_Ep03Done();
		if(dwIrqSource & D13REG_INTSRC_EP04)
			ISR_Ep04Done();
		if(dwIrqSource & D13REG_INTSRC_EP05)
			ISR_Ep05Done();
		if(dwIrqSource & D13REG_INTSRC_EP06)
			ISR_Ep06Done();
		if(dwIrqSource & D13REG_INTSRC_EP07)
			ISR_Ep07Done();
		if(dwIrqSource & D13REG_INTSRC_EP08)
			ISR_Ep08Done();
		if(dwIrqSource & D13REG_INTSRC_EP09)
			ISR_Ep09Done();
		if(dwIrqSource & D13REG_INTSRC_EP0A)
			ISR_Ep0ADone();
		if(dwIrqSource & D13REG_INTSRC_EP0B)
			ISR_Ep0BDone();
		if(dwIrqSource & D13REG_INTSRC_EP0C)
			ISR_Ep0CDone();
		if(dwIrqSource & D13REG_INTSRC_EP0D)
			ISR_Ep0DDone();
		if(dwIrqSource & D13REG_INTSRC_EP0E)
			ISR_Ep0EDone();
	}

	if(dwIrqSource & D13REG_INTSRC_BUSTATUS)
		D13_DevInfo.bits.BusStatus = 1;
	else
		D13_DevInfo.bits.BusStatus = 0;


	bIRQL = 0;
	if(dwIrqSource & 0xFFFFFF00)
		return TRUE;
	else
		return FALSE;

}

void ISR_BusReset(void)
{
	D13_DevInfo.bits.Event_BusReset = 1;
//	cprintf(" USB bus reset.\n");
}

void ISR_BusResume(void)
{
	D13_DevInfo.bits.Event_BusResume = 1;
//	cprintf(" USB bus resume.\n");
}

void ISR_SuspendChange(void)
{
	D13_DevInfo.bits.Event_Suspend = 1;
//	cprintf(" Suspend comes.\n");
}

void ISR_BusStatus(void)
{
	D13_DevInfo.bits.BusStatus = 1;     //1: suspend, 0: awake
}


void ISR_DmaEot(void)
{
	D13_DevInfo.bits.Event_EOT = 1;
//	cprintf("Error: EOT Missing.\n");
}

void ISR_PseudoSOF(void)
{
	D13_DevInfo.bits.Event_MissSOF = 1;
	D13_DevInfo.bits.Event_SOF = 0;		//wzw, 3-19-01
//	cprintf("Error: SOF Missing.\n");
}

void ISR_SOF(void)
{
	D13_DevInfo.bits.Event_SOF = 1;
//	cprintf(" SOF Coming.\n");
}

void ISR_Ep00RxDone(void)
{
	UCHAR       byEnpLastStatus;
	UCHAR		wXactionCounter;

	byEnpLastStatus = D13_GetEndpointStatusWInteruptClear(EPINDEX4EP0_CONTROL_OUT); /* Clear interrupt flag */

	if (!(byEnpLastStatus & D13REG_EPSTS_DBF0))

	{
		cprintf("Fatal Error: ISR_Ep00RxDone GetEndpointStatus=%x\n",byEnpLastStatus);
		return ;
	}

	if (byEnpLastStatus & D13REG_EPSTS_SETUP)
	{
		/*
		// Getting Setup Packet
		*/
		switch( DCPCtrlXfer.FSMState )
		{
		case USBFSM4DCP_SETUPPROC:
			/*
			// Abnormal case
			// Setup Transaction starts over the previous Setup Transaction.
			//
			*/
			/*
			// !!!Make sure fall thru!!!
			*/
		case USBFSM4DCP_DATAOUT:
			/*
			// Abnormal case
			// Setup Transaction starts within a broken transfer
			//
			// Host starts Setup Transaction in Data Out Stage of broken Control Transfer
			*/
			/*
			// !!!Make sure fall thru!!!
			*/
		case USBFSM4DCP_DATAIN:
			/*
			// Abnormal case
			// Setup Transaction starts within a broken transfer
			//
			// Host starts Setup Transaction in Data In Stage of broken Control Transfer
			*/
			/*
			// !!!Make sure fall thru!!!
			*/
		case USBFSM4DCP_REQUESTPROC:
			DCPCtrlXfer.bAbort = 1;
			/*
			// !!!Make sure fall thru!!!
			*/
		case USBFSM4DCP_HANDSHAKE:
		case USBFSM4DCP_STALL :
		case USBFSM4DCP_IDLE :
			DCPCtrlXfer.FSMState = USBFSM4DCP_SETUPPROC;	//Normal !!!
			break;
		default:
			/*
			// abnormal case
			// No such case
			*/
			cprintf("Fatal Error , Getting Setup Packet from UNKOWN state! =x%hx\n", DCPCtrlXfer.FSMState);
			DCPCtrlXfer.FSMState = USBFSM4DCP_SETUPPROC;
			break;
		}
	}
	else /* not a setup packet, just a Data Out Packet */
	{
		switch (DCPCtrlXfer.FSMState)
		{
		case USBFSM4DCP_DATAOUT:
			/*
			// Normal Path
			// Data out Stage of In Control Write Transfer.
			//
			// In the worst case,
			// if a Setup Packet came
			//  Because no AckSetup , No successive Data Out is allowed
			//  Because no StallEp0 , No stall will return.
			//
			*/
			wXactionCounter =	D13_ReadEndpoint(EPINDEX4EP0_CONTROL_OUT, DCPCtrlXfer.ptrBuf + (DCPCtrlXfer.wCount+1)/2,
				EP0_PACKET_SIZE);

			DCPCtrlXfer.wCount += wXactionCounter;
			if(  EP0_PACKET_SIZE != wXactionCounter || DCPCtrlXfer.wCount >= DCPCtrlXfer.wLength)
			{
				// Short Length Packet
				DCPCtrlXfer.FSMState = USBFSM4DCP_REQUESTPROC;
			} /* else  in state of USBFSM4DCP_DATAOUT */
			break;
		case USBFSM4DCP_HANDSHAKE:
			/*
			// it may or may not be zero Length Packet in the STATUS stage of Get Command,
			*/
			/*
			// According to USB1.1 8.5.2.1
			// Any Length Pkt issued by host is taken as valid status stage
			*/
			DCPCtrlXfer.FSMState = USBFSM4DCP_IDLE;
			/* D13 has Ack it in hardware, otherwise I cannot receive this interrupt*/
			break;

		case USBFSM4DCP_STALL:
			/*
			// After STALL,Except SETUP Token, No other token is allowed
			*/
			/* !!!Make sure FAll THRU!!! */
			break;
		case USBFSM4DCP_SETUPPROC:
			/*
			//In SETUPPROC, no Data-out phase shall occur.
			*/
			/* !!!Make sure FAll THRU!!! */
		case USBFSM4DCP_REQUESTPROC:

			/* !!!Make sure FAll THRU!!! */
	   case USBFSM4DCP_DATAIN:
			/*
			// Only IN token not Out Token is expected
			*/
			/* !!!Make sure FAll THRU!!! */
		default:
			/*
			// Anyway Stall it
			*/
			cprintf("Fatal Error: ISR_Ep0RxDone ReadLastTranactionStatus=%x\n",byEnpLastStatus);
			DCPCtrlXfer.FSMState = USBFSM4DCP_STALL;
			DcS_StallEP0InControlWrite();
			break;
		}
	}
	return ;
}

void ISR_Ep00TxDone(void)
{
	USHORT	wXferResidue = DCPCtrlXfer.wLength - DCPCtrlXfer.wCount;
	UCHAR	byEnpLastStatus;

	byEnpLastStatus = D13_GetEndpointStatusWInteruptClear(EPINDEX4EP0_CONTROL_IN); /* Clear interrupt flag */

	if ( byEnpLastStatus & D13REG_EPSTS_DBF0 )
	{
		cprintf("Fatal Error: ISR_Ep0TxDone ReadLastTranactionStatus=%x, status, %x\n",byEnpLastStatus, DCPCtrlXfer.FSMState);
		return;
	}

	switch (DCPCtrlXfer.FSMState)
	{
	case USBFSM4DCP_HANDSHAKE:
		break;
	case USBFSM4DCP_DATAIN:
		if( wXferResidue >= EP0_PACKET_SIZE)
		{
			D13_WriteEndpoint(EPINDEX4EP0_CONTROL_IN,DCPCtrlXfer.ptrBuf + (DCPCtrlXfer.wCount+1)/2, EP0_PACKET_SIZE);
			DCPCtrlXfer.wCount += EP0_PACKET_SIZE;

			/*
			// State remains at USBFSM4DCP_DATAIN
			*/
		}
		else if( 0 != wXferResidue )
		{
			D13_WriteEndpoint(1, DCPCtrlXfer.ptrBuf + (DCPCtrlXfer.wCount+1)/2, wXferResidue);
			DCPCtrlXfer.wCount += wXferResidue;

			/*
			// Go to Handshake state, let HOST send 0-length Pkt.
			*/
			DCPCtrlXfer.FSMState = USBFSM4DCP_HANDSHAKE;
			LowerIRQL();
		}
		else if (0 == wXferResidue )
		{
			/*
			// Go to Handshake state, let HOST send 0-length Pkt.
			*/
			//apend 0 length pkt,
			DcS_SingleTransmitEP0(0, 0);
			DCPCtrlXfer.FSMState = USBFSM4DCP_HANDSHAKE;
		}
		break;
	case USBFSM4DCP_REQUESTPROC:
	case USBFSM4DCP_IDLE:
	case USBFSM4DCP_SETUPPROC:
	case USBFSM4DCP_STALL:
	case USBFSM4DCP_DATAOUT:
	default:
		cprintf("Fatal Error: ISR_Ep0TxDone Unexpected FSMState=%x\n",DCPCtrlXfer.FSMState);
		DCPCtrlXfer.FSMState = USBFSM4DCP_STALL;
		DcS_StallEP0InControlRead();
		break;
	}
}

void ISR_Ep01Done(void)
{
	UCHAR  byEnpLastStatus;
	byEnpLastStatus = D13_GetEndpointStatusWInteruptClear(EPINDEX4EP01); /* Clear interrupt flag */
}


void ISR_Ep02Done(void)
{
	UCHAR  byEnpLastStatus;
	byEnpLastStatus = D13_GetEndpointStatusWInteruptClear(EPINDEX4EP02); /* Clear interrupt flag */

}

void ISR_Ep03Done(void)
{
	UCHAR  byEnpLastStatus;
	byEnpLastStatus = D13_GetEndpointStatusWInteruptClear(EPINDEX4EP03); /* Clear interrupt flag */
}


void ISR_Ep04Done(void)
{
	UCHAR  byEnpLastStatus;
	byEnpLastStatus = D13_GetEndpointStatusWInteruptClear(EPINDEX4EP04); /* Clear interrupt flag */

}

void ISR_Ep05Done(void)
{
	UCHAR  byEnpLastStatus;
	byEnpLastStatus = D13_GetEndpointStatusWInteruptClear(EPINDEX4EP05); /* Clear interrupt flag */
}


void ISR_Ep06Done(void)
{
	UCHAR  byEnpLastStatus;
	byEnpLastStatus = D13_GetEndpointStatusWInteruptClear(EPINDEX4EP06); /* Clear interrupt flag */

}

void ISR_Ep07Done(void)
{
	UCHAR  byEnpLastStatus;
	byEnpLastStatus = D13_GetEndpointStatusWInteruptClear(EPINDEX4EP07); /* Clear interrupt flag */
}


void ISR_Ep08Done(void)
{
	UCHAR  byEnpLastStatus;
	byEnpLastStatus = D13_GetEndpointStatusWInteruptClear(EPINDEX4EP08); /* Clear interrupt flag */

}

void ISR_Ep09Done(void)
{
	UCHAR  byEnpLastStatus;
	byEnpLastStatus = D13_GetEndpointStatusWInteruptClear(EPINDEX4EP09); /* Clear interrupt flag */

}

void ISR_Ep0ADone(void)
{
	UCHAR  byEnpLastStatus;
	byEnpLastStatus = D13_GetEndpointStatusWInteruptClear(EPINDEX4EP0A); /* Clear interrupt flag */
}


void ISR_Ep0BDone(void)
{
	UCHAR  byEnpLastStatus;
	byEnpLastStatus = D13_GetEndpointStatusWInteruptClear(EPINDEX4EP0B); /* Clear interrupt flag */

}

void ISR_Ep0CDone(void)
{
	UCHAR  byEnpLastStatus;
	byEnpLastStatus = D13_GetEndpointStatusWInteruptClear(EPINDEX4EP0C); /* Clear interrupt flag */
}


void ISR_Ep0DDone(void)
{
	UCHAR  byEnpLastStatus;
	byEnpLastStatus = D13_GetEndpointStatusWInteruptClear(EPINDEX4EP0D); /* Clear interrupt flag */

}


void ISR_Ep0EDone(void)
{
	UCHAR  byEnpLastStatus;
	byEnpLastStatus = D13_GetEndpointStatusWInteruptClear(EPINDEX4EP0E); /* Clear interrupt flag */

}