📄 d13_reg.h
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/*
//*************************************************************************
//
// P H I L I P S P R O P R I E T A R Y
//
// COPYRIGHT (c) 1999 BY PHILIPS SINGAPORE.
// -- ALL RIGHTS RESERVED --
//
// File Name: D13_REG.H
// Created: Feb 1, 2000
// Modified:
// Revision: 0.1
//
//*************************************************************************
//
//*************************************************************************
*/
#ifndef __D13_REG_H__
#define __D13_REG_H__
#define ISP1181_CHIPID
#define NONISO_FIFOSIZE_0 0
#define NONISO_FIFOSIZE_8 8
#define NONISO_FIFOSIZE_16 16
#define NONISO_FIFOSIZE_32 32
#define NONISO_FIFOSIZE_64 64
#define NONISO_FIFOSIZE_128 128
#define NONISO_FIFOSIZE_256 256
#define NONISO_FIFOSIZE_512 512
#define ISO_FIFOSIZE_0 0
#define ISO_FIFOSIZE_16 16
#define ISO_FIFOSIZE_32 32
#define ISO_FIFOSIZE_48 48
#define ISO_FIFOSIZE_64 64
#define ISO_FIFOSIZE_96 96
#define ISO_FIFOSIZE_128 128
#define ISO_FIFOSIZE_160 160
#define ISO_FIFOSIZE_192 192
#define ISO_FIFOSIZE_256 256
#define ISO_FIFOSIZE_320 320
#define ISO_FIFOSIZE_384 384
#define ISO_FIFOSIZE_512 512
#define ISO_FIFOSIZE_640 640
#define ISO_FIFOSIZE_768 768
#define ISO_FIFOSIZE_1023 1023
#define EP0_FIFO_SIZE NONISO_FIFOSIZE_64
#define EP0_PACKET_SIZE NONISO_FIFOSIZE_64
// 1181 Endpoint Index
#define EPINDEX4EP0_CONTROL_OUT 0x0
#define EPINDEX4EP0_CONTROL_IN 0x1
#define EPINDEX4EP01 0x2
#define EPINDEX4EP02 0x3
#define EPINDEX4EP03 0x4
#define EPINDEX4EP04 0x5
#define EPINDEX4EP05 0x6
#define EPINDEX4EP06 0x7
#define EPINDEX4EP07 0x8
#define EPINDEX4EP08 0x9
#define EPINDEX4EP09 0xA
#define EPINDEX4EP0A 0xB
#define EPINDEX4EP0B 0xC
#define EPINDEX4EP0C 0xD
#define EPINDEX4EP0D 0xE
#define EPINDEX4EP0E 0xF
// 1181 Command Set
#define D13CMD_DEV_RESET 0xF6
#define D13CMD_DEV_RD_CHIPID 0xB5
#define D13CMD_DEV_WR_ADDR 0xB6
#define D13CMD_DEV_RD_ADDR 0xB7
#define D13CMD_DEV_WR_MODE 0xB8
#define D13CMD_DEV_RD_MODE 0xB9
#define D13CMD_DEV_WR_CNFG 0xBA
#define D13CMD_DEV_RD_CNFG 0xBB
#define D13CMD_DEV_INT_SRC 0xC0
#define D13CMD_DEV_WR_INTEN 0xC2
#define D13CMD_DEV_RD_INTEN 0xC3
#define D13CMD_DEV_WR_RAM 0xB2
#define D13CMD_DEV_RD_RAM 0xB3
#define D13CMD_DEV_LOCK 0xB0
#define D13CMD_DMA_RD_COUNT 0xF3
#define D13CMD_DMA_WR_COUNT 0xF2
#define D13CMD_DMA_RD_CNFG 0xF1
#define D13CMD_DMA_WR_CNFG 0xF0
#define D13CMD_ACK_SETUP 0xF4
#define D13CMD_RD_FRMNUM 0xB4
#define D13CMD_EP_WR_FIFO 0x00
#define D13CMD_EP_RD_FIFO 0x10
#define D13CMD_EP_WR_CNFG 0x20
#define D13CMD_EP_RD_CNFG 0x30
#define D13CMD_EP_WR_STS 0x40 /* WR STS will set endpoint stall.*/
#define D13CMD_EP_CLR_STALL 0x80
#define D13CMD_EP_RDSTS_CLRINT 0x50
#define D13CMD_EP_VALID_BUF 0x60
#define D13CMD_EP_CLEAR_BUF 0x70
#define D13CMD_EP_RDSTS 0xD0
#define D13CMD_EP_RD_ERR 0xA0
// BMP for DevADDR
#define D13REG_DEVADDR_MASK 0x7F
#define D13REG_DEVADDR_EN 0x80
typedef struct _D13REG_DEVADDR{
UCHAR IsDevEnabled :1;
UCHAR DevAddr :7;
UCHAR Reserv0;
} D13REG_DEVADDR;
// BMP for EP_CNFG
#define D13REG_EPCNFG_FIFO_EN 0x80
#define D13REG_EPCNFG_IN_EN 0x40
#define D13REG_EPCNFG_DBLBUF_EN 0x20
#define D13REG_EPCNFG_ISO_EN 0x10
#define D13REG_EPCNFG_ISOSZ_MASK 0x0F
#define D13REG_EPCNFG_NONISOSZ_MASK 0x07
#define D13REG_EPCNFG_RFB_EN 0x08
typedef struct _D13REG_EPCNFG{
UCHAR FIFOSize :4;
UCHAR IsISO :1;
UCHAR IsDoubleBuf :1;
UCHAR IsOutEndp :1;
UCHAR IsFIFOEnabled :1;
UCHAR Reserv0;
} D13REG_EPCNFG;
//ww 14-02-00 FIFO size correction
//#define D13REG_EPCNFG_NONISOSZ_0 0x00
//#define D13REG_EPCNFG_NONISOSZ_8 0x01
//#define D13REG_EPCNFG_NONISOSZ_16 0x02
//#define D13REG_EPCNFG_NONISOSZ_32 0x03
//#define D13REG_EPCNFG_NONISOSZ_64 0x04
#define D13REG_EPCNFG_NONISOSZ_8 0x00
#define D13REG_EPCNFG_NONISOSZ_16 0x01
#define D13REG_EPCNFG_NONISOSZ_32 0x02
#define D13REG_EPCNFG_NONISOSZ_64 0x03
#define D13REG_EPCNFG_NONISOSZ_128 0x04
#define D13REG_EPCNFG_NONISOSZ_512 0x05
//#define D13REG_EPCNFG_NONISOSZ_512 0x06
//#define D13REG_EPCNFG_ISOSZ_0 0x00
#define D13REG_EPCNFG_ISOSZ_16 0x00
#define D13REG_EPCNFG_ISOSZ_32 0x01
#define D13REG_EPCNFG_ISOSZ_48 0x02
#define D13REG_EPCNFG_ISOSZ_64 0x03
#define D13REG_EPCNFG_ISOSZ_96 0x04
#define D13REG_EPCNFG_ISOSZ_128 0x05
#define D13REG_EPCNFG_ISOSZ_160 0x06
#define D13REG_EPCNFG_ISOSZ_192 0x07
#define D13REG_EPCNFG_ISOSZ_256 0x08
#define D13REG_EPCNFG_ISOSZ_320 0x09
#define D13REG_EPCNFG_ISOSZ_384 0x0A
#define D13REG_EPCNFG_ISOSZ_512 0x0B
#define D13REG_EPCNFG_ISOSZ_640 0x0C
#define D13REG_EPCNFG_ISOSZ_768 0x0D
#define D13REG_EPCNFG_ISOSZ_896 0x0E
#define D13REG_EPCNFG_ISOSZ_1023 0x0F
// BMP for EP_STATUS
#define D13REG_EPSTS_STALL 0x80
#define D13REG_EPSTS_DBF1 0x40
#define D13REG_EPSTS_DBF0 0x20
#define D13REG_EPSTS_OVWR 0x08
#define D13REG_EPSTS_SETUP 0x04
#define D13REG_EPSTS_DBFIDX 0x02
typedef struct _D13REG_EPSTS{
UCHAR bReserv0 :1;
UCHAR DBFIndex :1;
UCHAR IsSETUP :1;
UCHAR IsOverWritten :1;
UCHAR bReserv1 :1;
UCHAR IsBuf0Full :1;
UCHAR IsBuf1Full :1;
UCHAR IsStalled :1;
UCHAR Reserv0;
} D13REG_EPSTS;
// BMP for Error_Code
#define D13REG_ERRCODE_RXTX 0x01
#define D13REG_ERRCODE_DPID 0x40
#define D13REG_ERRCODE_OVRLP 0x80
#define D13REG_ERRCODE_MASK 0x1E
#define D13REG_ERRCODE_OK 0x00
#define D13REG_ERRCODE_PIDERR 0x02
#define D13REG_ERRCODE_PIDNEW 0x04
#define D13REG_ERRCODE_PKTTYP 0x06
#define D13REG_ERRCODE_TKCRC 0x08
#define D13REG_ERRCODE_DATACRC 0x0A
#define D13REG_ERRCODE_TIMEOUT 0x0C
#define D13REG_ERRCODE_RSRV0 0x0E
#define D13REG_ERRCODE_EOP 0x10
#define D13REG_ERRCODE_NAK 0x12
#define D13REG_ERRCODE_STALL 0x14
#define D13REG_ERRCODE_OVRFL 0x16
#define D13REG_ERRCODE_RSRV1 0x18
#define D13REG_ERRCODE_BITSTUFF 0x1A
#define D13REG_ERRCODE_RSRV2 0x1C
#define D13REG_ERRCODE_DATAPID 0x1E
typedef struct _D13REG_ERRCODE{
UCHAR IsOK :1;
UCHAR ErrorCode :4;
UCHAR bReserv0 :1;
UCHAR DataToggle :1;
UCHAR IsStatusOverwritten :1;
UCHAR Reserv0;
} D13REG_ERRCODE;
// BMP for UNLOCK_CMD
#define D13REG_UNLOCK_CODE 0xAA37
// BMP for MODE
#define D13REG_MODE_SOFTCONNECT 0x01
#define D13REG_MODE_OFFGOODLNK 0x02
#define D13REG_MODE_DBG 0x04
#define D13REG_MODE_INT_EN 0x08
#define D13REG_MODE_SUSPND 0x20
#define D13REG_MODE_RESUME 0x40
#define D13REG_MODE_DMA16 0x80
typedef struct _D13REG_MODE{
UCHAR SoftConnect :1;
UCHAR DisableGoodLink :1;
UCHAR DbgMode :1;
UCHAR EnableAllInterrupts :1;
UCHAR bReserv0 :1;
UCHAR GotoSuspend :1;
UCHAR SendResume :1;
UCHAR DMAWidth :1; /*Keeps it as 1 = 16bit always*/
UCHAR Reserv0;
} D13REG_MODE;
// BMP for 1181 CNFG
#define D13REG_DEVCNFG_INTPOL 0x0001
#define D13REG_DEVCNFG_INTLVL 0x0002
#define D13REG_DEVCNFG_PWROFF 0x0004
#define D13REG_DEVCNFG_WAKEUPBY_CS 0x0008
#define D13REG_DEVCNFG_EOTPOL 0x0010
#define D13REG_DEVCNFG_DMAACKPOL 0x0020
#define D13REG_DEVCNFG_DMARQPOL 0x0040
#define D13REG_DEVCNFG_DMAACKONLY 0x0080
#define D13REG_DEVCNFG_CLOCKDIV_MASK 0x0F00
#define D13REG_DEVCNFG_CLOCKRUNNING 0x1000
#define D13REG_DEVCNFG_NOLAZYCLOCK 0x2000
#define D13REG_DEVCNFG_EXPULLUP 0x4000
typedef struct _D13REG_DEVCNFG{
UCHAR IsIrqActiveHi :1;
UCHAR IsIrqEdgeTrigged :1;
UCHAR EnablePwrSwitch :1;
UCHAR EnableCSWakeup :1;
UCHAR IsEOTActiveHi :1;
UCHAR IsDACKActiveHi :1;
UCHAR IsDREQActiveHi :1;
UCHAR IsDACKOnlyMode :1;
UCHAR ClockDividor :4;
UCHAR Keep48MhzOn :1;
UCHAR NoLazyClk :1;
UCHAR ExternalPullup :1;
UCHAR bReserv0 :1;
} D13REG_DEVCNFG;
#define D13REG_DEVCNFG_CLOCKDIV_480M 0x0000
#define D13REG_DEVCNFG_CLOCKDIV_240M 0x0100
#define D13REG_DEVCNFG_CLOCKDIV_160M 0x0200
#define D13REG_DEVCNFG_CLOCKDIV_120M 0x0300
#define D13REG_DEVCNFG_CLOCKDIV_96M 0x0400
#define D13REG_DEVCNFG_CLOCKDIV_80M 0x0500
#define D13REG_DEVCNFG_CLOCKDIV_69M 0x0600
#define D13REG_DEVCNFG_CLOCKDIV_60M 0x0700
#define D13REG_DEVCNFG_CLOCKDIV_54M 0x0800
#define D13REG_DEVCNFG_CLOCKDIV_48M 0x0900
#define D13REG_DEVCNFG_CLOCKDIV_44M 0x0A00
#define D13REG_DEVCNFG_CLOCKDIV_40M 0x0B00
#define D13REG_DEVCNFG_CLOCKDIV_37M 0x0C00
#define D13REG_DEVCNFG_CLOCKDIV_34M 0x0D00
#define D13REG_DEVCNFG_CLOCKDIV_32M 0x0E00
#define D13REG_DEVCNFG_CLOCKDIV_30M 0x0F00
// BMP for INTERRUPT SRC
#define D13REG_INTSRC_BUSRESET 0x000001
#define D13REG_INTSRC_RESUME 0x000002
#define D13REG_INTSRC_SUSPEND 0x000004
#define D13REG_INTSRC_EOT 0x000008
#define D13REG_INTSRC_SOF 0x000010
#define D13REG_INTSRC_PSEUDO_SOF 0x000020
#define D13REG_INTSRC_BUSTATUS 0x000080
#define D13REG_INTSRC_EP0OUT 0x000100
#define D13REG_INTSRC_EP0IN 0x000200
#define D13REG_INTSRC_EP01 0x000400
#define D13REG_INTSRC_EP02 0x000800
#define D13REG_INTSRC_EP03 0x001000
#define D13REG_INTSRC_EP04 0x002000
#define D13REG_INTSRC_EP05 0x004000
#define D13REG_INTSRC_EP06 0x008000
#define D13REG_INTSRC_EP07 0x010000
#define D13REG_INTSRC_EP08 0x020000
#define D13REG_INTSRC_EP09 0x040000
#define D13REG_INTSRC_EP0A 0x080000
#define D13REG_INTSRC_EP0B 0x100000
#define D13REG_INTSRC_EP0C 0x200000
#define D13REG_INTSRC_EP0D 0x400000
#define D13REG_INTSRC_EP0E 0x800000
typedef struct _D13REG_INTSRC{
UCHAR Reset :1;
UCHAR Resume :1;
UCHAR Suspend :1;
UCHAR EOT :1;
UCHAR SOF :1;
UCHAR PseudoSOF :1;
UCHAR bReserv0 :1;
UCHAR StatusChange :1;
UCHAR EP0OUT :1;
UCHAR EP0IN :1;
UCHAR EP1 :1;
UCHAR EP2 :1;
UCHAR EP3 :1;
UCHAR EP4 :1;
UCHAR EP5 :1;
UCHAR EP6 :1;
UCHAR EP7 :1;
UCHAR EP8 :1;
UCHAR EP9 :1;
UCHAR EP10 :1;
UCHAR EP11 :1;
UCHAR EP12 :1;
UCHAR EP13 :1;
UCHAR EP14 :1;
UCHAR Reserv0;
} D13REG_INTSRC;
// BMP for DMA Cnfg
#define D13REG_DMACNFG_BURSTLEN_MASK 0x0003
#define D13REG_DMACNFG_AUTOLOAD 0x0004
#define D13REG_DMACNFG_ENABLE 0x0008
#define D13REG_DMACNFG_EPINDX_MASK 0x00F0
#define D13REG_DMACNFG_NONISOPKTSZ_MASK 0x1F00
#define D13REG_DMACNFG_NONISOPKTSZ_EN 0x2000
#define D13REG_DMACNFG_EOTBY_SHORTPKT_EN 0x4000
#define D13REG_DMACNFG_COUNTER_EN 0x8000
#define D13REG_DMACNFG_BURSTLEN0 0x0000
#define D13REG_DMACNFG_BURSTLEN4 0x0001
#define D13REG_DMACNFG_BURSTLEN8 0x0002
#define D13REG_DMACNFG_BURSTLEN16 0x0003
typedef struct _D13REG_DMACNFG{
UCHAR BurstLength :2;
UCHAR AutoLoad :1;
UCHAR EnableDMA :1;
UCHAR TargetEndpIndx :4;
UCHAR bReserv0 :6;
UCHAR EnableEOT4ShortPkt :1;
UCHAR EnableEOT4Counter :1;
} D13REG_DMACNFG;
//*************************************************************************
// Member Functions
//*************************************************************************
void D13_SWResetDevice(void);
USHORT D13_ReadChipID(void);
USHORT D13_GetDataFromChipRam(void);
void D13_SetDataToChipRam(USHORT wData);
void D13_UnlockDevice(void);
// Irq
void D13_SetIntEnable(ULONG dwIntEn);
ULONG D13_GetIntEnable(void);
ULONG D13_ReadInterruptRegister(void);
// DMA
USHORT D13_GetDMAConfig(void);
void D13_SetDMAConfig(USHORT wDMAConfig);
USHORT D13_GetDMACounter(void);
void D13_SetDMACounter(USHORT wDMACounter);
// Per Dev
void D13_SetDevConfig(USHORT wDevCnfg);
USHORT D13_GetDevConfig(void);
UCHAR D13_GetMode(void);
void D13_SetMode(UCHAR byMode);
void D13_SoftConnect(UCHAR byEnable);
void D13_SendResume(void);
void D13_SetAddressEnable(UCHAR byAddress, UCHAR byEnable);
UCHAR D13_GetAddress(void);
// Per Control endpoint
void D13_AcknowledgeSETUP(void );
USHORT D13_ReadCurrentFrameNumber(void);
// Per Endpoint Index
UCHAR D13_GetEndpointConfig(UCHAR byEPIndex);
void D13_SetEndpointConfig(UCHAR byEPConfig, UCHAR byEPIndex);
UCHAR D13_GetErrorCode(UCHAR byEPIndex);
UCHAR D13_GetEndpointStatusWInteruptClear(UCHAR byEPIndex);
UCHAR D13_GetEndpointStatusWOInteruptClear(UCHAR byEPIndex);
void D13_SetEndpointStatus(UCHAR byEPIndex, UCHAR byStalled);
void D13_ClearBuffer(UCHAR byEPIndex);
void D13_ValidBuffer(UCHAR byEPIndex);
USHORT D13_ReadEndpoint(UCHAR byEPIndex, USHORT * ptrBuf, USHORT wLength);
USHORT D13_WriteEndpoint(UCHAR byEPIndex, USHORT * ptrBuf, USHORT wLength);
USHORT D13_ReadEndpointWOClearBuffer(UCHAR byEPIndex, USHORT * ptrBuf, USHORT wLength);
USHORT D13_ReadEndpointWOValidBuffer(UCHAR byEPIndex, USHORT * ptrBuf, USHORT wLength);
USHORT D13_ReadEndpoint2IO(UCHAR byEPIndex, USHORT wIoPort, USHORT wLength);
USHORT D13_WriteEndpoint2IO(UCHAR byEPIndex, USHORT IoPort, USHORT wLength);
UCHAR D13_Endp2EndpIndex(UCHAR byEndpoint);
UCHAR D13_EndpIndex2Endp(UCHAR byEndpointIndex);
#endif
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