📄 d13_dcs.c
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/*
//*************************************************************************
//
// P H I L I P S P R O P R I E T A R Y
//
// COPYRIGHT (c) 1999 BY PHILIPS SINGAPORE.
// -- ALL RIGHTS RESERVED --
//
// File Name: D13_DcS.C
// Created: Feb. 1, 2000
// Modified: May 23,2002 by Zhongwei Wang
// Revision: 0.9
//
//*************************************************************************
//
//*************************************************************************
*/
#include <dos.h>
#include <stdio.h>
#include "SysCnfg.h"
#include "BasicTyp.h"
#include "DcCommon.h"
#include "HAL4Sys.h"
#include "Hal4ISA.h"
#include "Hal4IKit.h"
#include "Hal4D13.h"
#include "D13_Reg.h"
#include "D13_DcS.h"
#include "usb100.h"
/*
//*************************************************************************
// Public static data
//*************************************************************************
*/
extern UCHAR bIRQL;
extern ISP1362_PCIKIT;
/*
//*************************************************************************
// Private static data
//*************************************************************************
*/
void interrupt (*D13_OldIsr4D13)(void);
/*
//*************************************************************************
// Subroutines -- 1
//*************************************************************************
*/
void DcS_AcquireD13(void)
{
RaiseIRQL();
bIRQL = 1;
Hal4ISA_AcquireIRQ4D13();
Hal4ISA_AcquireDMA4D13();
Hal4ISA_AcquirePIO4D13();
// DcS_ConfigEndpoint();
DcS_InitD13();
bIRQL = 0;
LowerIRQL();
}
void DcS_ReleaseD13(void)
{
RaiseIRQL();
bIRQL = 1;
D13_SWResetDevice();
Hal4ISA_ReleasePIO4D13();
Hal4ISA_ReleaseDMA4D13();
Hal4ISA_ReleaseIRQ4D13();
bIRQL = 0;
LowerIRQL();
}
void DcS_ConfigDevice(void)
{
}
void DcS_UnconfigDevice(void)
{
}
void DcS_SingleTransmitEP0(USHORT * ptrBuf, USHORT wLength)
{
if( wLength <= EP0_PACKET_SIZE) {
D13_WriteEndpoint(EPINDEX4EP0_CONTROL_IN, ptrBuf, wLength);
}
}
void DcS_DumpReg(void)
{
UCHAR c;
USHORT i;
ULONG l;
D13_SWResetDevice();
printf("Reseting\n");
i = D13_ReadChipID();
printf("1181 ChipId = %hx\n",i);
i = D13_GetDataFromChipRam();
printf("1181 Chip RAM = %hx\n",i);
printf("Writing 0x55AA,");
D13_SetDataToChipRam(0x55AA);
i = D13_GetDataFromChipRam();
printf("1181 Chip RAM = %hx\n",i);
l = D13_GetIntEnable();
printf("D13_GetIntEnable = %lx\n",l);
l = D13_ReadInterruptRegister();
printf("D13_ReadInterruptRegister = %lx\n",l);
i = D13_GetDevConfig();
printf("D13_GetDevConfig = %hx\n",i);
i = D13_GetDMAConfig();
printf("D13_GetDMAConfig = %hx\n",i);
i = D13_GetDMACounter();
printf("D13_GetDMACounter = %hx\n",i);
i = D13_ReadCurrentFrameNumber();
printf("D13_ReadCurrentFrameNumber = %hx\n",i);
c = D13_GetMode();
printf("D13_GetMode = %x\n",c);
c = D13_GetEndpointStatusWOInteruptClear(EPINDEX4EP0_CONTROL_OUT);
printf("D13_GetEndpointStatus EP0 = %x\n",c);
c = D13_GetAddress();
printf("D13_GetAddress = %x\n",c);
}
void DcS_StallEP0InControlWrite(void)
{
D13_SetEndpointStatus(EPINDEX4EP0_CONTROL_IN, D13REG_EPSTS_STALL);
D13_SetEndpointStatus(EPINDEX4EP0_CONTROL_OUT, D13REG_EPSTS_STALL);
}
void DcS_StallEP0InControlRead(void)
{
D13_SetEndpointStatus(EPINDEX4EP0_CONTROL_OUT, D13REG_EPSTS_STALL);
D13_SetEndpointStatus(EPINDEX4EP0_CONTROL_IN, D13REG_EPSTS_STALL);
}
BOOLEAN DcS_IsAnyNewSetupPkt(void)
{
UCHAR NewSetupPacket;
NewSetupPacket = D13_GetEndpointStatusWOInteruptClear(EPINDEX4EP0_CONTROL_OUT)&D13REG_EPSTS_SETUP;
return NewSetupPacket;
}
BOOLEAN DcS_IsSetupPktInvalid(void)
{
UCHAR SetupPacketInvalid;
SetupPacketInvalid = D13_GetEndpointStatusWOInteruptClear(EPINDEX4EP0_CONTROL_OUT)&D13REG_EPSTS_OVWR;
return SetupPacketInvalid;
}
void DcS_DisconnectUSB(void)
{
/*
// Initialize D13 configuration
*/
/* D13_SetDevConfig( \
D13REG_DEVCNFG_INTPOL| \
D13REG_DEVCNFG_PWROFF| \
D13REG_DEVCNFG_NOLAZYCLOCK| \
D13REG_DEVCNFG_CLOCKRUNNING);*/
D13_SetMode(0);
}
void DcS_Connect2USB(void)
{
DcS_InitD13();
D13_SetMode(D13REG_MODE_INT_EN|D13REG_MODE_SOFTCONNECT);
}
void DcS_Reconnect2USB(void)
{
DcS_DisconnectUSB();
Hal4Sys_WaitinUS(5); // SE0 > 2.5uS USB1.1
DcS_Connect2USB();
}
void DcS_ConfigEndpoint(void)
{
// ULONG dwData = 0;
// Note: all 16 endpoints should be included in the initialization sequence,
// include CONTOL_IN, CONTROL_OUT and endp1-14
D13_SetEndpointConfig(D13REG_EPCNFG_FIFO_EN|D13REG_EPCNFG_NONISOSZ_64,EPINDEX4EP0_CONTROL_OUT);
D13_SetEndpointConfig(D13REG_EPCNFG_FIFO_EN|D13REG_EPCNFG_IN_EN|D13REG_EPCNFG_NONISOSZ_64,EPINDEX4EP0_CONTROL_IN);
D13_SetEndpointConfig(D13REG_EPCNFG_FIFO_EN|D13REG_EPCNFG_NONISOSZ_8,EPINDEX4EP01);
D13_SetEndpointConfig(D13REG_EPCNFG_FIFO_EN|D13REG_EPCNFG_IN_EN|D13REG_EPCNFG_NONISOSZ_8,EPINDEX4EP02);
D13_SetEndpointConfig(D13REG_EPCNFG_FIFO_EN|D13REG_EPCNFG_DBLBUF_EN|D13REG_EPCNFG_NONISOSZ_8,EPINDEX4EP03);
D13_SetEndpointConfig(D13REG_EPCNFG_FIFO_EN|D13REG_EPCNFG_DBLBUF_EN|D13REG_EPCNFG_IN_EN|D13REG_EPCNFG_NONISOSZ_8,EPINDEX4EP04);
D13_SetEndpointConfig(D13REG_EPCNFG_FIFO_EN|D13REG_EPCNFG_DBLBUF_EN|D13REG_EPCNFG_ISOSZ_16|D13REG_EPCNFG_ISO_EN,EPINDEX4EP05);
D13_SetEndpointConfig(D13REG_EPCNFG_FIFO_EN|D13REG_EPCNFG_IN_EN|D13REG_EPCNFG_DBLBUF_EN|D13REG_EPCNFG_ISOSZ_16|D13REG_EPCNFG_ISO_EN,EPINDEX4EP06);
D13_SetEndpointConfig(0,EPINDEX4EP07);
D13_SetEndpointConfig(0,EPINDEX4EP08);
D13_SetEndpointConfig(0,EPINDEX4EP09);
D13_SetEndpointConfig(0,EPINDEX4EP0A);
D13_SetEndpointConfig(0,EPINDEX4EP0B);
D13_SetEndpointConfig(0,EPINDEX4EP0C);
D13_SetEndpointConfig(0,EPINDEX4EP0D);
D13_SetEndpointConfig(0,EPINDEX4EP0E);
}
void DcS_InitD13(void)
{
D13_SWResetDevice();
Hal4Sys_WaitinMS(20);
DcS_ConfigEndpoint();
D13_SetIntEnable( \
D13REG_INTSRC_EP0OUT|\
D13REG_INTSRC_EP0IN |\
D13REG_INTSRC_EP03| \
D13REG_INTSRC_EP04 |\
// D13REG_INTSRC_SOF | \
// D13REG_INTSRC_PSEUDO_SOF | \
D13REG_INTSRC_SUSPEND |\
D13REG_INTSRC_RESUME |\
D13REG_INTSRC_BUSRESET);
if( ISP1362_PCIKIT ) //ISA kit: INT2 active high. PCI kit:INT2 active low
D13_SetDevConfig(0 \
//INT2 level trigged, active high
// | D13REG_DEVCNFG_INTPOL \
//SUSPEND output pin active high. must set to '1' for ISP1362
| D13REG_DEVCNFG_PWROFF \
| D13REG_DEVCNFG_NOLAZYCLOCK \
| D13REG_DEVCNFG_CLOCKDIV_60M \
// | D13REG_DEVCNFG_CLOCKRUNNING \
//active high (keep low if not used, FPGA hardware limitation)
| D13REG_DEVCNFG_DMARQPOL \
//1.5k pull-up controlled by OTG register, SoftConnect bit in DC not function
| D13REG_DEVCNFG_EXPULLUP \
);
else //ISA kit
D13_SetDevConfig(0 \
//INT2 level trigged, active high
| D13REG_DEVCNFG_INTPOL \
//SUSPEND output pin active high. must set to '1' for ISP1362
| D13REG_DEVCNFG_PWROFF \
| D13REG_DEVCNFG_NOLAZYCLOCK \
| D13REG_DEVCNFG_CLOCKDIV_60M \
// | D13REG_DEVCNFG_CLOCKRUNNING \
//active high (keep low if not used, FPGA hardware limitation)
| D13REG_DEVCNFG_DMARQPOL \
//1.5k pull-up controlled by OTG register, SoftConnect bit in DC not function
| D13REG_DEVCNFG_EXPULLUP \
);
}
void DcS_EnableIRQ(void)
{
//enable writing registers
D13_UnlockDevice();
//clear existing interrupts
D13_ReadInterruptRegister();
Hal4Sys_WaitinUS(10);
D13_ReadInterruptRegister();
Hal4Sys_WaitinUS(10);
//enable interrupt for DC
D13_SetMode(D13_GetMode() | D13REG_MODE_INT_EN);
}
void DcS_DisableIRQ(void)
{
//clear existing interrupts
D13_ReadInterruptRegister();
Hal4Sys_WaitinUS(10);
D13_ReadInterruptRegister();
Hal4Sys_WaitinUS(10);
//disable interrupt for DC
D13_SetMode(D13_GetMode() & ~D13REG_MODE_INT_EN);
}
void DcS_GoSuspend(void)
{
D13_SetMode(D13_GetMode() | D13REG_MODE_SUSPND);
Hal4Sys_WaitinUS(2);
D13_SetMode(D13_GetMode() & ~D13REG_MODE_SUSPND);
Hal4Sys_WaitinMS(10); //allow clock down
}
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