📄 phc_reg.h
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/*
//*************************************************************************
//
// P H I L I P S P R O P R I E T A R Y
//
// COPYRIGHT (c) 2000 BY PHILIPS SINGAPORE.
// -- ALL RIGHTS RESERVED --
//
// File Name: PHC_Reg.h
// Author: ZhenYu Zhang
// Created: Jun. 8, 2000
// Modified:
// Revision: 0.0
//
//*************************************************************************
// Notes:
// PHC_xx : Philips Host Controller
//
//*************************************************************************
*/
#ifndef __PHC_REG_H__
#define __PHC_REG_H__
// 16bit PIO Reg
#define REG_HW_MODE 0x20
#define REG_DMA_CNFG 0x21
#define REG_XFER_CNTR 0x22
#define REG_IRQ 0x24
#define REG_IRQ_MASK 0x25
#define REG_CHIP_ID 0x27
#define REG_SCRATCH 0x28
#define REG_RESET_DEV 0xA9
//#define REG_ITL_BUFLEN 0x2A
//#define REG_ATL_BUFLEN 0x2B
#define REG_BUFF_STS 0x2C
//#define REG_ITL0_LEN 0x2D
//#define REG_ITL1_LEN 0x2E
//#define REG_ITL_BUFF_IO 0x40
//16bit PIO Reg for ISP1362
//Buffer Control Registers
#define REG_DIRECT_ADDRESS_LENGTH 0x32
#define REG_DIRECT_ADDRESS_DATA 0x45
//ATL registers
//#define REG_ATL_BUFF_IO 0x41
#define REG_ATL_BUFF_SIZE 0x34
#define REG_ATL_BUFF_IO 0x44
#define REG_ATL_BLK_SIZE 0x54
#define REG_ATL_PTD_DONE_MAP 0x1B
#define REG_ATL_PTD_SKIP_MAP 0x1C
#define REG_ATL_LAST_PTD 0x1D
#define REG_ATL_CURR_ACT_PTD 0x1E
#define REG_ATL_PTD_DONE_TH_COUNT 0x51
#define REG_ATL_PTD_DONE_TH_TIMEOUT 0x52
//INTL registers
#define REG_INTL_BUFF_SIZE 0x33
#define REG_INTL_BUFF_IO 0x43
#define REG_INTL_BLK_SIZE 0x53
#define REG_INTL_PTD_DONE_MAP 0x17
#define REG_INTL_PTD_SKIP_MAP 0x18
#define REG_INTL_LAST_PTD 0x19
#define REG_INTL_CURR_ACT_PTD 0x1A
//ISTL registers
#define REG_ISTL_BUFF_SIZE 0x30
#define REG_ISTL0_BUFF_IO 0x40
#define REG_ISTL1_BUFF_IO 0x42
#define REG_ISTL_TOGGLE_RATE 0x47
//#define REG_HW_MODE 0x20
#define RHM_I_MIE 0x0001
#define RHM_I_PULSE 0x0002
#define RHM_I_POLARITY 0x0004
#define RHM_DB_16 0x0008
#define RHM_DB_32 0x0010
#define RHM_DREQ_POLARITY 0x0020
#define RHM_DACK_POLARITY 0x0040
#define RHM_EOT_POLARITY 0x0080
#define RHM_DACK_ONLY 0x0100
#define RHM_OC_EN 0x0400
#define RHM_CLK_RUN 0x0800
#define RHM_PULLDOWN 0x1000
//#define REG_DMA_CNFG 0x21
//#define REG_XFER_CNTR 0x22
//#define REG_IRQ 0x24
#define RI_SOF 0x0001
#define RI_ATL 0x0002
#define RI_EOT 0x0004
#define RI_RESERV0 0x0008
#define RI_PHC 0x0010
#define RI_SUSP 0x0020
#define RI_CLKRDY 0x0040
#define RI_OTG 0x0200
//#define REG_IRQ_MASK 0x25
#define RIM_SOF 0x0001
#define RIM_ATL 0x0002
#define RIM_EOT 0x0004
#define RIM_RESERV0 0x0008
#define RIM_PHC 0x0010
#define RIM_SUSP 0x0020
#define RIM_CLKRDY 0x0040
#define RIM_OTG 0x0200
//#define REG_CHIP_ID 0x27
//#define REG_SCRATCH 0x28
//#define REG_RESET_DEV 0xA9
//#define REG_ITL_BUFLEN 0x2A
//#define REG_ATL_BUFLEN 0x2B
//#define REG_BUFF_STS 0x2C
#define RBS_ISOA_FULL 0x01
#define RBS_ISOB_FULL 0x02
#define RBS_ATL_FULL 0x04
#define RBS_ISOA_DONE 0x08
#define RBS_ISOB_DONE 0x10
#define RBS_ATL_DONE 0x20
//#define REG_ITL0_LEN 0x2D
//#define REG_ITL1_LEN 0x2E
//#define REG_ITL_BUFF_IO 0x40
//#define REG_ATL_BUFF_IO 0x41
// 32 bit SLH Reg
#define SLHREG_REVISION 0x00
#define SLHREG_CONTROL 0x01
#define SLHREG_COMMAND 0x02
#define SLHREG_INT_STS 0X03
#define SLHREG_INT_EN 0x04
#define SLHREG_INT_DIS 0x05
#define SLHREG_FRM_INTERVAL 0x0D
#define SLHREG_FRM_REMAIN 0x0E
#define SLHREG_FRM_NUMBER 0x0F
#define SLHREG_FRM_LS_THRESH 0x11
#define SLHREG_RH_DESCRIP_A 0x12
#define SLHREG_RH_DESCRIP_B 0x13
#define SLHREG_RH_STATUS 0X14
#define SLHREG_RH_PORTSTATUS1 0x15
#define SLHREG_RH_PORTSTATUS2 0x16
#define RH_PORT1 0x01
#define RH_PORT2 0x02
//#define SLHREG_REVISION 0x00
typedef union _SLH_REVISION_REG {
struct {
USHORT Revision : 8;
USHORT Reserv0 : 8;
USHORT Reserv1 ;
} Bits;
ULONG L0;
} SLH_REVISION_REG, * PSLH_REVISION_REG;
//#define SLHREG_CONTROL 0x01
typedef union _SLH_CONTROL_REG {
struct {
USHORT Reserv0 : 6;
USHORT HcFuncState : 2;
USHORT Reserv1 : 1;
USHORT RemoteWakeupConnect : 1;
USHORT RemoteWakeupEnable : 1;
USHORT Reserv2 : 5;
USHORT Reserv3 ;
} Bits;
ULONG L0;
} SLH_CONTROL_REG, * PSLH_CONTROL_REG;
#define SLHR_CTRL_HCFS_RESET 0x00
#define SLHR_CTRL_HCFS_RESUME 0x01
#define SLHR_CTRL_HCFS_OP 0x02
#define SLHR_CTRL_HCFS_SUSP 0x03
//#define SLHREG_COMMAND 0x02
typedef union _SLH_COMMAND_REG {
struct {
USHORT SoftReset : 1;
USHORT Reserv0 : 5;
USHORT ScheduleOverrunCount : 2;
USHORT Reserv1 : 8;
USHORT Reserv2 ;
} Bits;
ULONG L0;
} SLH_COMMAND_REG, * PSLH_COMMAND_REG;
//#define SLHREG_INT_STS 0X03
typedef union _SLH_INTSTS_REG {
struct {
USHORT ScheduleOverrun : 1;
USHORT ATLisDone : 1;
USHORT SOF : 1;
USHORT ResumeDeteced : 1;
USHORT FatalError : 1;
USHORT FrameNumOverflow : 1;
USHORT RootHubStatusChange : 1;
USHORT Reserv0 : 9;
USHORT Reserv1 ;
} Bits;
ULONG L0;
} SLH_INTSTS_REG, * PSLH_INTSTS_REG;
//#define SLHREG_INT_EN 0x04
typedef union _SLH_INTEN_REG {
struct {
USHORT ScheduleOverrun : 1;
USHORT ATLisDone : 1;
USHORT SOF : 1;
USHORT ResumeDeteced : 1;
USHORT FatalError : 1;
USHORT FrameNumOverflow : 1;
USHORT RootHubStatusChange : 1;
USHORT Reserv0 : 9;
USHORT Reserv1 : 15;
USHORT MasterInterrupt : 1;
} Bits;
ULONG L0;
} SLH_INTEN_REG, * PSLH_INTEN_REG;
//#define SLHREG_INT_DIS 0x05
typedef union _SLH_INTDIS_REG {
struct {
USHORT ScheduleOverrun : 1;
USHORT ATLisDone : 1;
USHORT SOF : 1;
USHORT ResumeDeteced : 1;
USHORT FatalError : 1;
USHORT FrameNumOverflow : 1;
USHORT RootHubStatusChange : 1;
USHORT Reserv0 : 9;
USHORT Reserv1 : 15;
USHORT MasterInterrupt : 1;
} Bits;
ULONG L0;
} SLH_INTDIS_REG, * PSLH_INTDIS_REG;
//#define SLHREG_FRM_INTERVAL 0x0D
typedef union _SLH_FRMINTVL_REG {
struct {
USHORT FrameInterval : 14;
USHORT Reserv0 : 2;
USHORT FrameLargestPktSize : 15;
USHORT FrameIntervalToggel : 1;
} Bits;
ULONG L0;
} SLH_FRMINTVL_REG, * PSLH_FRMINTVL_REG;
//#define SLHREG_FRM_REMAIN 0x0E
typedef union _SLH_FRMREM_REG {
struct {
USHORT FrameRemaining : 14;
USHORT Reserv0 : 2;
USHORT Reserv11 : 15;
USHORT FrameRemainToggel : 1;
} Bits;
ULONG L0;
} SLH_FRMREM_REG, * PSLH_FRMREM_REG;
//#define SLHREG_FRM_NUMBER 0x0F
typedef union _SLH_FRMNUM_REG {
struct {
USHORT FrameNumber ;
USHORT Reserv0 ;
} Bits;
ULONG L0;
} SLH_FRMNUM_REG, * PSLH_FRMNUM_REG;
//#define SLHREG_FRM_LS_THRESH 0x11
typedef union _SLH_FRLS_THRESH_REG {
struct {
USHORT LSThreshold : 12;
USHORT Reserv0 : 4;
USHORT Reserv1 ;
} Bits;
ULONG L0;
} SLH_FRMLS_THRESH_REG, * PSLH_FRMLS_THRESH_REG;
//#define SLHREG_RH_DESCRIP_A 0x12
typedef union _SLH_RH_DESCA_REG {
struct {
USHORT NumOfDnPorts : 8;
USHORT PowerSwitchMode : 1;
USHORT NoPowerSwitch : 1;
USHORT DeviceType : 1;
USHORT OvrCurProtectMode : 1;
USHORT NoOvrCurProtect : 1;
USHORT Reserv0 : 3;
USHORT Reserv1 : 8;
USHORT PowerOn2PowerGoodTime : 8;
} Bits;
ULONG L0;
} SLH_RH_DESCA_REG, * PSLH_RH_DESCA_REG;
#define PHC_DNPORTS_MAX 0x02
//#define SLHREG_RH_DESCRIP_B 0x13
typedef union _SLH_RH_DESCB_REG {
struct {
USHORT DeviceRemovableMap ;
USHORT PortPowerControlMask ;
} Bits;
ULONG L0;
} SLH_RH_DESCB_REG, * PSLH_RH_DESCB_REG;
//#define SLHREG_RH_STATUS 0X14
typedef union _SLH_RH_STATUS_REG {
struct {
USHORT LocalPowerStatus : 1;
USHORT OvrCurIndicator : 1;
USHORT Reserv0 : 13;
USHORT DeviceRemoteWakupEnable : 1;
USHORT LocalPowerStatusChange : 1;
USHORT OvrCurIndicatorChange : 1;
USHORT Reserv1 : 13;
USHORT ClearRemoteWakeupEnable : 1;
} Bits;
ULONG L0;
} SLH_RH_STS_REG, * PSLH_RH_STS_REG;
//#define SLHREG_RH_PORTSTATUS1 0x15
//#define SLHREG_RH_PORTSTATUS2 0x16
typedef union _SLH_RH_PORTSTATUS_REG {
struct {
USHORT CurrentConnectStatus : 1;
USHORT PortEnableStatus : 1;
USHORT PortSuspendStatus : 1;
USHORT PortOvrCurIndicator : 1;
USHORT PortResetStatus : 1;
USHORT Reserv0 : 3;
USHORT PortPowerStatus : 1;
USHORT LSDeviceAttached : 1;
USHORT Reserv1 : 6;
USHORT CurrentConnectStatusChange : 1;
USHORT PortEnableStatusChange : 1;
USHORT PortSuspendStatusChange : 1;
USHORT PortOvrCurIndicatorChange : 1;
USHORT PortResetStatusChange : 1;
USHORT Reserv2 : 11;
} Bits;
ULONG L0;
} SLH_RH_PORTSTS_REG, * PSLH_RH_PORTSTS_REG;
typedef union _SLH_RH_PORTSTATUS_WR_REG {
struct {
USHORT ClearPortEnable : 1;
USHORT SetPortEnable : 1;
USHORT SetPortSuspend : 1;
USHORT ClearPortSuspend : 1;
USHORT SetPortReset : 1;
USHORT Reserv0 : 3;
USHORT SetPortPower : 1;
USHORT ClearPortPower : 1;
USHORT Reserv1 : 6;
USHORT ClearConnectStatusChange : 1;
USHORT ClearPortStatusChange : 1;
USHORT ClearPortSuspendStatusChange : 1;
USHORT ClearPortOvrCurIndicatorChange : 1;
USHORT ClearPortResetStatusChange : 1;
USHORT Reserv2 : 11;
} Bits;
ULONG L0;
} SLH_RH_PORTSTS_WR_REG, * PSLH_RH_PORTSTS_WR_REG;
typedef union _Flexi_ULONG {
ULONG FlexLong;
SLH_REVISION_REG SlhRevsion;
SLH_CONTROL_REG SlhControl;
SLH_COMMAND_REG SlhCommand;
SLH_INTSTS_REG SlhIntStatus;
SLH_INTEN_REG SlhIntEnable;
SLH_INTDIS_REG SlhIntDisable;
SLH_FRMINTVL_REG SlhFrameInterval;
SLH_FRMREM_REG SlhFrameRemain;
SLH_FRMNUM_REG SlhFrameNumber;
SLH_FRMLS_THRESH_REG SlhFrameLSThreashold;
SLH_RH_DESCA_REG SlhRootHubDescriptorA;
SLH_RH_DESCB_REG SlhRootHubDescriptorB;
SLH_RH_STS_REG SlhRootHubStatus;
SLH_RH_PORTSTS_REG SlhRootHubPortStatus;
SLH_RH_PORTSTS_WR_REG SlhRootHubPortStatusWr;
} SLH_REG_ULONG, * PSLH_REG_ULONG;
/*
//*************************************************************************
// Subroutines - PHC_xxx
//*************************************************************************
*/
ULONG PHC_GetRevision(void);
void PHC_Control(ULONG dwBits);
ULONG PHC_GetControlState( void );
void PHC_Command(ULONG dwBits);
ULONG PHC_GetCommandState( void );
ULONG PHC_GetInterruptStatus( void );
void PHC_ClearInterrupts(ULONG dwBits );
void PHC_DisableInterrupts(ULONG dwBits );
void PHC_EnableInterrupts(ULONG dwBits );
ULONG PHC_GetInterruptMask( void );
void PHC_ConfigFrame(ULONG dwBits);
ULONG PHC_GetFrameConfig(void);
ULONG PHC_GetFrameRem(void);
ULONG PHC_GetFrameNum(void);
void PHC_ConfigLSThreashold(ULONG dwBits);
ULONG PHC_GetLSThreashold(void);
void PHC_ConfigRootHubDescA(ULONG dwBits);
ULONG PHC_GetRootHubDescA( void);
void PHC_ConfigRootHubDescB(ULONG dwBits);
ULONG PHC_GetRootHubDescB( void);
void PHC_SetRootHub( ULONG dwBits);
ULONG PHC_GetRootHubStatus( void );
void PHC_SetRootHubPort(UCHAR DnPort, ULONG dwBits);
ULONG PHC_GetRootHubPortStatus(UCHAR DnPort);
/*
//*************************************************************************
// Subroutines - SHC_xxx
//*************************************************************************
*/
void PHC_SetXferCounter( USHORT XferLengthInByte);
USHORT PHC_GetBufferStatus(void);
void PHC_Wait4ATLDone(void);
void PHC_Wait4ITLDone(void);
void PHC_ResetPort(UCHAR DnPort);
void PHC_DisablePort(UCHAR DnPort);
void PHC_EnablePort(UCHAR DnPort);
ULONG PHC_PollInterruptStatus(void);
ULONG PHC_PollRootHub(void);
ULONG PHC_PollRootHubPort(UCHAR PortNum);
USHORT PHC_GetATLPTDDoneMap(void);
#endif
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