s3c2410.h

A tone driver by driving S3c2410 PWM. Compiled by arm-linux-gcc.

#define NFCONF_TACLS     FMsk(fNFCONF_TACLS)
#define NFCONF_TACLS_0   FInsrt(0x0, fNFCONF_TACLS) /* 0 */
#define fNFCONF_nFCE     Fld(1,11)
#define NFCONF_nFCE      FMsk(fNFCONF_nFCE)
#define NFCONF_nFCE_LOW  FInsrt(0x0, fNFCONF_nFCE) /* active */
#define NFCONF_nFCE_HIGH FInsrt(0x1, fNFCONF_nFCE) /* inactive */
#define fNFCONF_ECC      Fld(1,12)
#define NFCONF_ECC       FMsk(fNFCONF_ECC)
#define NFCONF_ECC_NINIT FInsrt(0x0, fNFCONF_ECC) /* not initialize */
#define NFCONF_ECC_INIT  FInsrt(0x1, fNFCONF_ECC)    /* initialize */
#define fNFCONF_ADDRSTEP Fld(1,13)                 /* Addressing Step */
#define NFCONF_ADDRSTEP  FMsk(fNFCONF_ADDRSTEP)
#define fNFCONF_PAGESIZE Fld(1,14)
#define NFCONF_PAGESIZE  FMsk(fNFCONF_PAGESIZE)
#define NFCONF_PAGESIZE_256  FInsrt(0x0, fNFCONF_PAGESIZE) /* 256 bytes */
#define NFCONF_PAGESIZE_512  FInsrt(0x1, fNFCONF_PAGESIZE) /* 512 bytes */
#define fNFCONF_FCTRL    Fld(1,15)  /* Flash controller enable/disable */
#define NFCONF_FCTRL     FMsk(fNFCONF_FCTRL)
#define NFCONF_FCTRL_DIS FInsrt(0x0, fNFCONF_FCTRL) /* Disable */
#define NFCONF_FCTRL_EN  FInsrt(0x1, fNFCONF_FCTRL) /* Enable */

#define NFSTAT_RnB      (1 << 0)
#define NFSTAT_nFWE     (1 << 8)
#define NFSTAT_nFRE     (1 << 9)
#define NFSTAT_ALE      (1 << 10)
#define NFSTAT_CLE      (1 << 11)
#define NFSTAT_AUTOBOOT (1 << 15)


// UART
#define rULCON0     (*(volatile unsigned *)(VA_UART_BASE+0x00)) //UART 0 Line control
#define rUCON0      (*(volatile unsigned *)(VA_UART_BASE+0x04)) //UART 0 Control
#define rUFCON0     (*(volatile unsigned *)(VA_UART_BASE+0x08)) //UART 0 FIFO control
#define rUMCON0     (*(volatile unsigned *)(VA_UART_BASE+0x0c)) //UART 0 Modem control
#define rUTRSTAT0   (*(volatile unsigned *)(VA_UART_BASE+0x10)) //UART 0 Tx/Rx status
#define rUERSTAT0   (*(volatile unsigned *)(VA_UART_BASE+0x14)) //UART 0 Rx error status
#define rUFSTAT0    (*(volatile unsigned *)(VA_UART_BASE+0x18)) //UART 0 FIFO status
#define rUMSTAT0    (*(volatile unsigned *)(VA_UART_BASE+0x1c)) //UART 0 Modem status
#define rUBRDIV0    (*(volatile unsigned *)(VA_UART_BASE+0x28)) //UART 0 Baud rate divisor

#define rULCON1     (*(volatile unsigned *)(VA_UART_BASE+0x4000)) //UART 1 Line control
#define rUCON1      (*(volatile unsigned *)(VA_UART_BASE+0x4004)) //UART 1 Control
#define rUFCON1     (*(volatile unsigned *)(VA_UART_BASE+0x4008)) //UART 1 FIFO control
#define rUMCON1     (*(volatile unsigned *)(VA_UART_BASE+0x400c)) //UART 1 Modem control
#define rUTRSTAT1   (*(volatile unsigned *)(VA_UART_BASE+0x4010)) //UART 1 Tx/Rx status
#define rUERSTAT1   (*(volatile unsigned *)(VA_UART_BASE+0x4014)) //UART 1 Rx error status
#define rUFSTAT1    (*(volatile unsigned *)(VA_UART_BASE+0x4018)) //UART 1 FIFO status
#define rUMSTAT1    (*(volatile unsigned *)(VA_UART_BASE+0x401c)) //UART 1 Modem status
#define rUBRDIV1    (*(volatile unsigned *)(VA_UART_BASE+0x4028)) //UART 1 Baud rate divisor

#define rULCON2     (*(volatile unsigned *)(VA_UART_BASE+0x8000)) //UART 2 Line control
#define rUCON2      (*(volatile unsigned *)(VA_UART_BASE+0x8004)) //UART 2 Control
#define rUFCON2     (*(volatile unsigned *)(VA_UART_BASE+0x8008)) //UART 2 FIFO control
#define rUMCON2     (*(volatile unsigned *)(VA_UART_BASE+0x800c)) //UART 2 Modem control
#define rUTRSTAT2   (*(volatile unsigned *)(VA_UART_BASE+0x8010)) //UART 2 Tx/Rx status
#define rUERSTAT2   (*(volatile unsigned *)(VA_UART_BASE+0x8014)) //UART 2 Rx error status
#define rUFSTAT2    (*(volatile unsigned *)(VA_UART_BASE+0x8018)) //UART 2 FIFO status
#define rUMSTAT2    (*(volatile unsigned *)(VA_UART_BASE+0x801c)) //UART 2 Modem status
#define rUBRDIV2    (*(volatile unsigned *)(VA_UART_BASE+0x8028)) //UART 2 Baud rate divisor

#ifdef __BIG_ENDIAN
#define rUTXH0      (*(volatile unsigned char *)(VA_UART_BASE+0x23)) //UART 0 Transmission Hold
#define rURXH0      (*(volatile unsigned char *)(VA_UART_BASE+0x27)) //UART 0 Receive buffer
#define rUTXH1      (*(volatile unsigned char *)(VA_UART_BASE+0x4023)) //UART 1 Transmission Hold
#define rURXH1      (*(volatile unsigned char *)(VA_UART_BASE+0x4027)) //UART 1 Receive buffer
#define rUTXH2      (*(volatile unsigned char *)(VA_UART_BASE+0x8023)) //UART 2 Transmission Hold
#define rURXH2      (*(volatile unsigned char *)(VA_UART_BASE+0x8027)) //UART 2 Receive buffer

#define WrUTXH0(ch) (*(volatile unsigned char *)(VA_UART_BASE+0x23))=(unsigned char)(ch)
#define RdURXH0()   (*(volatile unsigned char *)(VA_UART_BASE+0x27))
#define WrUTXH1(ch) (*(volatile unsigned char *)(VA_UART_BASE+0x4023))=(unsigned char)(ch)
#define RdURXH1()   (*(volatile unsigned char *)(VA_UART_BASE+0x4027))
#define WrUTXH2(ch) (*(volatile unsigned char *)(VA_UART_BASE+0x8023))=(unsigned char)(ch)
#define RdURXH2()   (*(volatile unsigned char *)(VA_UART_BASE+0x8027))

#define UTXH0       (VA_UART_BASE+0x20+3)  //Byte_access address by DMA
#define URXH0       (VA_UART_BASE+0x24+3)
#define UTXH1       (VA_UART_BASE+0x4020+3)
#define URXH1       (VA_UART_BASE+0x4024+3)
#define UTXH2       (VA_UART_BASE+0x8020+3)
#define URXH2       (VA_UART_BASE+0x8024+3)

#else //Little Endian
#define rUTXH0 (*(volatile unsigned char *)(VA_UART_BASE+0x20)) //UART 0 Transmission Hold
#define rURXH0 (*(volatile unsigned char *)(VA_UART_BASE+0x24)) //UART 0 Receive buffer
#define rUTXH1 (*(volatile unsigned char *)(VA_UART_BASE+0x4020)) //UART 1 Transmission Hold
#define rURXH1 (*(volatile unsigned char *)(VA_UART_BASE+0x4024)) //UART 1 Receive buffer
#define rUTXH2 (*(volatile unsigned char *)(VA_UART_BASE+0x8020)) //UART 2 Transmission Hold
#define rURXH2 (*(volatile unsigned char *)(VA_UART_BASE+0x8024)) //UART 2 Receive buffer

#define WrUTXH0(ch) (*(volatile unsigned char *)(VA_UART_BASE+0x20))=(unsigned char)(ch)
#define RdURXH0()   (*(volatile unsigned char *)(VA_UART_BASE+0x24))
#define WrUTXH1(ch) (*(volatile unsigned char *)(VA_UART_BASE+0x4020))=(unsigned char)(ch)
#define RdURXH1()   (*(volatile unsigned char *)(VA_UART_BASE+0x4024))
#define WrUTXH2(ch) (*(volatile unsigned char *)(VA_UART_BASE+0x8020))=(unsigned char)(ch)
#define RdURXH2()   (*(volatile unsigned char *)(VA_UART_BASE+0x8024))

#define UTXH0       (VA_UART_BASE+0x20)    //Byte_access address by DMA
#define URXH0       (VA_UART_BASE+0x24)
#define UTXH1       (VA_UART_BASE+0x4020)
#define URXH1       (VA_UART_BASE+0x4024)
#define UTXH2       (VA_UART_BASE+0x8020)
#define URXH2       (VA_UART_BASE+0x8024)
#endif


// PWM TIMER
#define rTCFG0  (*(volatile unsigned *)(VA_TIMER_BASE+0x00)) //Timer 0 configuration
#define rTCFG1  (*(volatile unsigned *)(VA_TIMER_BASE+0x04)) //Timer 1 configuration
#define rTCON   (*(volatile unsigned *)(VA_TIMER_BASE+0x08)) //Timer control
#define rTCNTB0 (*(volatile unsigned *)(VA_TIMER_BASE+0x0c)) //Timer count buffer 0
#define rTCMPB0 (*(volatile unsigned *)(VA_TIMER_BASE+0x10)) //Timer compare buffer 0
#define rTCNTO0 (*(volatile unsigned *)(VA_TIMER_BASE+0x14)) //Timer count observation 0
#define rTCNTB1 (*(volatile unsigned *)(VA_TIMER_BASE+0x18)) //Timer count buffer 1
#define rTCMPB1 (*(volatile unsigned *)(VA_TIMER_BASE+0x1c)) //Timer compare buffer 1
#define rTCNTO1 (*(volatile unsigned *)(VA_TIMER_BASE+0x20)) //Timer count observation 1
#define rTCNTB2 (*(volatile unsigned *)(VA_TIMER_BASE+0x24)) //Timer count buffer 2
#define rTCMPB2 (*(volatile unsigned *)(VA_TIMER_BASE+0x28)) //Timer compare buffer 2
#define rTCNTO2 (*(volatile unsigned *)(VA_TIMER_BASE+0x2c)) //Timer count observation 2
#define rTCNTB3 (*(volatile unsigned *)(VA_TIMER_BASE+0x30)) //Timer count buffer 3
#define rTCMPB3 (*(volatile unsigned *)(VA_TIMER_BASE+0x34)) //Timer compare buffer 3
#define rTCNTO3 (*(volatile unsigned *)(VA_TIMER_BASE+0x38)) //Timer count observation 3
#define rTCNTB4 (*(volatile unsigned *)(VA_TIMER_BASE+0x3c)) //Timer count buffer 4
#define rTCNTO4 (*(volatile unsigned *)(VA_TIMER_BASE+0x40)) //Timer count observation 4

/* Searching Keyword: OS_Timer */
#define SYS_TIMER234_PRESCALER  202
#define SYS_TIMER01_PRESCALER   24      /* for Touch Screen  */

#define SYS_TIMER4_MUX          1	/* 1/4  */
#define SYS_TIMER4_DIVIDER      4 

#define SYS_TIMER1_MUX          0	/* 1/2  */
#define SYS_TIMER1_DIVIDER      2 

/* RTC will use TIMER 0  for periodic signal */
#define SYS_TIMER0_MUX          3	/* 1/2  */
#define SYS_TIMER0_DIVIDER      16

#define TOUCH_RESCHED_PERIOD    10      /* 10 ms */
#define RESCHED_PERIOD          10      /* 10 ms */
#define HZ                      100


// USB DEVICE
#ifdef __BIG_ENDIAN
<ERROR IF BIG_ENDIAN>
#define rFUNC_ADDR_REG     (*(volatile unsigned char *)(VA_UD_BASE+0x143)) //Function address
#define rPWR_REG           (*(volatile unsigned char *)(VA_UD_BASE+0x147)) //Power management
#define rEP_INT_REG        (*(volatile unsigned char *)(VA_UD_BASE+0x14b)) //EP Interrupt pending and clear
#define rUSB_INT_REG       (*(volatile unsigned char *)(VA_UD_BASE+0x15b)) //USB Interrupt pending and clear
#define rEP_INT_EN_REG     (*(volatile unsigned char *)(VA_UD_BASE+0x15f)) //Interrupt enable
#define rUSB_INT_EN_REG    (*(volatile unsigned char *)(VA_UD_BASE+0x16f))
#define rFRAME_NUM1_REG    (*(volatile unsigned char *)(VA_UD_BASE+0x173)) //Frame number lower byte
#define rFRAME_NUM2_REG    (*(volatile unsigned char *)(VA_UD_BASE+0x177)) //Frame number higher byte
#define rINDEX_REG         (*(volatile unsigned char *)(VA_UD_BASE+0x17b)) //Register index
#define rMAXP_REG          (*(volatile unsigned char *)(VA_UD_BASE+0x183)) //Endpoint max packet
#define rEP0_CSR           (*(volatile unsigned char *)(VA_UD_BASE+0x187)) //Endpoint 0 status
#define rIN_CSR1_REG       (*(volatile unsigned char *)(VA_UD_BASE+0x187)) //In endpoint control status
#define rIN_CSR2_REG       (*(volatile unsigned char *)(VA_UD_BASE+0x18b))
#define rOUT_CSR1_REG      (*(volatile unsigned char *)(VA_UD_BASE+0x193) //Out endpoint control status
#define rOUT_CSR2_REG      (*(volatile unsigned char *)(VA_UD_BASE+0x197))
#define rOUT_FIFO_CNT1_REG (*(volatile unsigned char *)(VA_UD_BASE+0x19b)) //Endpoint out write count
#define rOUT_FIFO_CNT2_REG (*(volatile unsigned char *)(VA_UD_BASE+0x19f))
#define rEP0_FIFO          (*(volatile unsigned char *)(VA_UD_BASE+0x1c3)) //Endpoint 0 FIFO
#define rEP1_FIFO          (*(volatile unsigned char *)(VA_UD_BASE+0x1c7)) //Endpoint 1 FIFO
#define rEP2_FIFO          (*(volatile unsigned char *)(VA_UD_BASE+0x1cb)) //Endpoint 2 FIFO
#define rEP3_FIFO          (*(volatile unsigned char *)(VA_UD_BASE+0x1cf)) //Endpoint 3 FIFO
#define rEP4_FIFO          (*(volatile unsigned char *)(VA_UD_BASE+0x1d3)) //Endpoint 4 FIFO
#define rEP1_DMA_CON       (*(volatile unsigned char *)(VA_UD_BASE+0x203)) //EP1 DMA interface control
#define rEP1_DMA_UNIT      (*(volatile unsigned char *)(VA_UD_BASE+0x207)) //EP1 DMA Tx unit counter
#define rEP1_DMA_FIFO      (*(volatile unsigned char *)(VA_UD_BASE+0x20b)) //EP1 DMA Tx FIFO counter
#define rEP1_DMA_TTC_L     (*(volatile unsigned char *)(VA_UD_BASE+0x20f)) //EP1 DMA total Tx counter
#define rEP1_DMA_TTC_M     (*(volatile unsigned char *)(VA_UD_BASE+0x213))
#define rEP1_DMA_TTC_H     (*(volatile unsigned char *)(VA_UD_BASE+0x217))
#define rEP2_DMA_CON       (*(volatile unsigned char *)(VA_UD_BASE+0x21b)) //EP2 DMA interface control
#define rEP2_DMA_UNIT      (*(volatile unsigned char *)(VA_UD_BASE+0x21f)) //EP2 DMA Tx unit counter
#define rEP2_DMA_FIFO      (*(volatile unsigned char *)(VA_UD_BASE+0x223)) //EP2 DMA Tx FIFO counter
#define rEP2_DMA_TTC_L     (*(volatile unsigned char *)(VA_UD_BASE+0x227)) //EP2 DMA total Tx counter
#define rEP2_DMA_TTC_M     (*(volatile unsigned char *)(VA_UD_BASE+0x22b)
#define rEP2_DMA_TTC_H     (*(volatile unsigned char *)(VA_UD_BASE+0x22f)
#define rEP3_DMA_CON       (*(volatile unsigned char *)(VA_UD_BASE+0x243)) //EP3 DMA interface control
#define rEP3_DMA_UNIT      (*(volatile unsigned char *)(VA_UD_BASE+0x247)) //EP3 DMA Tx unit counter
#define rEP3_DMA_FIFO      (*(volatile unsigned char *)(VA_UD_BASE+0x24b)) //EP3 DMA Tx FIFO counter
#define rEP3_DMA_TTC_L     (*(volatile unsigned char *)(VA_UD_BASE+0x24f)) //EP3 DMA total Tx counter
#define rEP3_DMA_TTC_M     (*(volatile unsigned char *)(VA_UD_BASE+0x253))
#define rEP3_DMA_TTC_H     (*(volatile unsigned char *)(VA_UD_BASE+0x257))
#define rEP4_DMA_CON       (*(volatile unsigned char *)(VA_UD_BASE+0x25b)) //EP4 DMA interface control
#define rEP4_DMA_UNIT      (*(volatile unsigned char *)(VA_UD_BASE+0x25f)) //EP4 DMA Tx unit counter
#define rEP4_DMA_FIFO      (*(volatile unsigned char *)(VA_UD_BASE+0x263)) //EP4 DMA Tx FIFO counter
#define rEP4_DMA_TTC_L     (*(volatile unsigned char *)(VA_UD_BASE+0x267)) //EP4 DMA total Tx counter
#define rEP4_DMA_TTC_M     (*(volatile unsigned char *)(VA_UD_BASE+0x26b))
#define rEP4_DMA_TTC_H     (*(volatile unsigned char *)(VA_UD_BASE+0x26f))

#else  // Little Endian
#define rFUNC_ADDR_REG     (*(volatile unsigned char *)(VA_UD_BASE+0x140)) //Function address
#define rPWR_REG           (*(volatile unsigned char *)(VA_UD_BASE+0x144)) //Power management
#define rEP_INT_REG        (*(volatile unsigned char *)(VA_UD_BASE+0x148)) //EP Interrupt pending and clear
#define rUSB_INT_REG       (*(volatile unsigned char *)(VA_UD_BASE+0x158)) //USB Interrupt pending and clear
#define rEP_INT_EN_REG     (*(volatile unsigned char *)(VA_UD_BASE+0x15c)) //Interrupt enable
#define rUSB_INT_EN_REG    (*(volatile unsigned char *)(VA_UD_BASE+0x16c))
#define rFRAME_NUM1_REG    (*(volatile unsigned char *)(VA_UD_BASE+0x170)) //Frame number lower byte
#define rFRAME_NUM2_REG    (*(volatile unsigned char *)(VA_UD_BASE+0x174)) //Frame number higher byte
#define rINDEX_REG         (*(volatile unsigned char *)(VA_UD_BASE+0x178)) //Register index
#define rMAXP_REG          (*(volatile unsigned char *)(VA_UD_BASE+0x180)) //Endpoint max packet
#define rEP0_CSR           (*(volatile unsigned char *)(VA_UD_BASE+0x184)) //Endpoint 0 status
#define rIN_CSR1_REG       (*(volatile unsigned char *)(VA_UD_BASE+0x184)) //In endpoint control status
#define rIN_CSR2_REG       (*(volatile unsigned char *)(VA_UD_BASE+0x188))
#define rOUT_CSR1_REG      (*(volatile unsigned char *)(VA_UD_BASE+0x190)) //Out endpoint control status
#define rOUT_CSR2_REG      (*(volatile unsigned char *)(VA_UD_BASE+0x194))
#define rOUT_FIFO_CNT1_REG (*(volatile unsigned char *)(VA_UD_BASE+0x198)) //Endpoint out write count
#define rOUT_FIFO_CNT2_REG (*(volatile unsigned char *)(VA_UD_BASE+0x19c))
#define rEP0_FIFO          (*(volatile unsigned char *)(VA_UD_BASE+0x1c0)) //Endpoint 0 FIFO
#define rEP1_FIFO          (*(volatile unsigned char *)(VA_UD_BASE+0x1c4)) //Endpoint 1 FIFO
#define rEP2_FIFO          (*(volatile unsigned char *)(VA_UD_BASE+0x1c8)) //Endpoint 2 FIFO
#define rEP3_FIFO          (*(volatile unsigned char *)(VA_UD_BASE+0x1cc)) //Endpoint 3 FIFO
#define rEP4_FIFO          (*(volatile unsigned char *)(VA_UD_BASE+0x1d0)) //Endpoint 4 FIFO
#define rEP1_DMA_CON       (*(volatile unsigned char *)(VA_UD_BASE+0x200)) //EP1 DMA interface control
#define rEP1_DMA_UNIT      (*(volatile unsigned char *)(VA_UD_BASE+0x204)) //EP1 DMA Tx unit counter
#define rEP1_DMA_FIFO      (*(volatile unsigned char *)(VA_UD_BASE+0x208)) //EP1 DMA Tx FIFO counter
#define rEP1_DMA_TTC_L     (*(volatile unsigned char *)(VA_UD_BASE+0x20c)) //EP1 DMA total Tx counter
#define rEP1_DMA_TTC_M     (*(volatile unsigned char *)(VA_UD_BASE+0x210))
#define rEP1_DMA_TTC_H     (*(volatile unsigned char *)(VA_UD_BASE+0x214))
#define rEP2_DMA_CON       (*(volatile unsigned char *)(VA_UD_BASE+0x218)) //EP2 DMA interface control
#define rEP2_DMA_UNIT      (*(volatile unsigned char *)(VA_UD_BASE+0x21c)) //EP2 DMA Tx unit counter
#define rEP2_DMA_FIFO      (*(volatile unsigned char *)(VA_UD_BASE+0x220)) //EP2 DMA Tx FIFO counter
#define rEP2_DMA_TTC_L     (*(volatile unsigned char *)(VA_UD_BASE+0x224)) //EP2 DMA total Tx counter
#define rEP2_DMA_TTC_M     (*(volatile unsigned char *)(VA_UD_BASE+0x228))
#define rEP2_DMA_TTC_H     (*(volatile unsigned char *)(VA_UD_BASE+0x22c))
#define rEP3_DMA_CON       (*(volatile unsigned char *)(VA_UD_BASE+0x240)) //EP3 DMA interface control
#define rEP3_DMA_UNIT      (*(volatile unsigned char *)(VA_UD_BASE+0x244)) //EP3 DMA Tx unit counter
#define rEP3_DMA_FIFO      (*(volatile unsigned char *)(VA_UD_BASE+0x248)) //EP3 DMA Tx FIFO counter
#define rEP3_DMA_TTC_L     (*(volatile unsigned char *)(VA_UD_BASE+0x24c)) //EP3 DMA total Tx counter
#define rEP3_DMA_TTC_M     (*(volatile unsigned char *)(VA_UD_BASE+0x250))
#define rEP3_DMA_TTC_H     (*(volatile unsigned char *)(VA_UD_BASE+0x254))
#define rEP4_DMA_CON       (*(volatile unsigned char *)(VA_UD_BASE+0x258)) //EP4 DMA interface control
#define rEP4_DMA_UNIT      (*(volatile unsigned char *)(VA_UD_BASE+0x25c)) //EP4 DMA Tx unit counter
#define rEP4_DMA_FIFO      (*(volatile unsigned char *)(VA_UD_BASE+0x260)) //EP4 DMA Tx FIFO counter
#define rEP4_DMA_TTC_L     (*(volatile unsigned char *)(VA_UD_BASE+0x264)) //EP4 DMA total Tx counter
#define rEP4_DMA_TTC_M     (*(volatile unsigned char *)(VA_UD_BASE+0x268))
#define rEP4_DMA_TTC_H     (*(volatile unsigned char *)(VA_UD_BASE+0x26c))
#endif   // __BIG_ENDIAN


// WATCH DOG TIMER
#define rWTCON   (*(volatile unsigned *)(VA_WD_BASE+0x00)) //Watch-dog timer mode
#define rWTDAT   (*(volatile unsigned *)(VA_WD_BASE+0x04)) //Watch-dog timer data
#define rWTCNT   (*(volatile unsigned *)(VA_WD_BASE+0x08)) //Eatch-dog timer count


// IIC
#define rIICCON  (*(volatile unsigned *)(VA_IIC_BASE+0x00)) //IIC control
#define rIICSTAT (*(volatile unsigned *)(VA_IIC_BASE+0x04)) //IIC status
#define rIICADD  (*(volatile unsigned *)(VA_IIC_BASE+0x08)) //IIC address
#define rIICDS   (*(volatile unsigned *)(VA_IIC_BASE+0x0c)) //IIC data shift


// IIS
#define rIISCON  (*(volatile unsigned *)(VA_IIS_BASE+0x00)) //IIS Control
#define rIISMOD  (*(volatile unsigned *)(VA_IIS_BASE+0x04)) //IIS Mode
#define rIISPSR  (*(volatile unsigned *)(VA_IIS_BASE+0x08)) //IIS Prescaler
#define rIISFCON (*(volatile unsigned *)(VA_IIS_BASE+0x0c)) //IIS FIFO control