s3c2410.h

A tone driver by driving S3c2410 PWM. Compiled by arm-linux-gcc.

/*
 *  linux/include/asm-arm/arch-s3c2410/s3c2410.h
 *
 *  Copyright (C) 2002 SAMSUNG ELECTORNICS 
 *                         SW.LEE ([e-mail])
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 */

/* Contents of This File 
 * 1.Clock Parameter  
 *      
 * 2.Register Mapping
 * 3.Physical to Virtual Mapping 
 *                     Searching Keyword: Phy2Vir
 * 4.Serial Baud Rate 
 *                     Searching Keyword: SER_BAUD
 * 5.OS Timer Parameter
 *                     Searching Keyword: OS_Timer 
 * 6.Sound clock       Searching Keyword: CODEC_CLOCK 
 *
 */


#ifndef __S3C2410_H
#define __S3C2410_H

#ifndef LANGUAGE
# ifdef __ASSEMBLY__
#  define LANGUAGE Assembly
# else
#  define LANGUAGE C
# endif
#endif


//#include "bitfield.h"


/* keywoard : ClockParameter */
/***************  Clock Parameter  **********/
#define  FCLK 202800000
#define  HCLK (FCLK/2)
#define  PCLK (HCLK/2)
#define  UCLK  48000000
#define  BUSWIDTH (32)
/********************************************/



/* keywoard : Phy2Vir */
#define S3C2410_MEM_SIZE     (64*1024*1024) 
#define MEM_SIZE            S3C2410_MEM_SIZE
	/* Used in arm/kernel/setup.c */

                        /* used in asm/kernel/setup.c and asm/arch/arch.c  */
#define PA_SDRAM_BASE         0x30000000 /* used in asm/arch/arch.c     */
#define RAMDISK_DN_ADDR       0x30800000 /* used in asm/arch/arch.c     */
#define ZIP_RAMDISK_SIZE      (10*1024*1024)  /* used in asm/arch/arch.c  */

/* if CONFIG_BLK_DEV_RAM_SIZE not defined */
#define BLK_DEV_RAM_SIZE      (8*1024*1024)  


/*** S3C2410 Register Address Part ***************************
 *If you change this mapping between Physical and Virtual
 *YOU MUST CHNAGE MACRO in the include/asm/arch-s3c2410/memory.h
 * ex) __Distance_PA_VA
 *and also SDRAM Mapping must be changed becasue __Distance_PA_VA is
 * applied to IO Register and SDRAM
 */ 

/* Be careful !!!!
 * PAGE_OFFSET + VMALLOC_END = 0xD0000000
 */

#define VA_IO_BASE0           (0xD0000000)
#define VA_IO_BASE1           (0xE0000000)
#define VA_IO_BASE2           (0xD8000000) /* CS8900A */

#define io_p2v(x) ((x) |  0x98000000)		/* peripheral */
#define io_v2p(x) ((x) & ~0x98000000)



#define PA_MEM_CTR_BASE       (0x48000000)/* used int asm/arch/mm.c */
#define VA_MEM_CTR_BASE       (VA_IO_BASE0+0x08000000)
#define PA_USB_BASE           (0x49000000)
#define VA_USB_BASE           (VA_IO_BASE0+0x09000000)
#define PA_INT_BASE           (0x4A000000)
#define VA_INT_BASE           (VA_IO_BASE0+0x0A000000)
#define PA_DMA_BASE           (0x4B000000)
#define VA_DMA_BASE           (VA_IO_BASE0+0x0B000000)
#define PA_CKPO_BASE          (0x4C000000)
#define VA_CKPO_BASE          (VA_IO_BASE0+0x0C000000)
#define PA_LCD_BASE           (0x4D000000)
#define VA_LCD_BASE           (VA_IO_BASE0+0x0D000000)
#define PA_NAND_BASE          (0x4E000000)
#define VA_NAND_BASE          (VA_IO_BASE0+0x0E000000)
#define PA_UART_BASE          (0x50000000)
#define VA_UART_BASE          (VA_IO_BASE1+0x00000000)
#define PA_TIMER_BASE         (0x51000000)
#define VA_TIMER_BASE         (VA_IO_BASE1+0x01000000)
#define PA_UD_BASE            (0x52000000)	/* WATCH DOG AND USB DEVICE */
#define VA_UD_BASE            (VA_IO_BASE1+0x02000000)	/* WATCH DOG AND USB DEVICE */
#define PA_WD_BASE            (0x53000000)
#define VA_WD_BASE            (VA_IO_BASE1+0x03000000)
#define PA_IIC_BASE           (0x54000000)
#define VA_IIC_BASE           (VA_IO_BASE1+0x04000000)
#define PA_IIS_BASE           (0x55000000)
#define VA_IIS_BASE           (VA_IO_BASE1+0x05000000)
#define PA_IO_PORT_BASE       (0x56000000)
#define VA_IO_PORT_BASE       (VA_IO_BASE1+0x06000000)
#define PA_RTC_BASE           (0x57000000)
#define VA_RTC_BASE           (VA_IO_BASE1+0x07000000)
#define PA_ADC_BASE           (0x58000000)
#define VA_ADC_BASE           (VA_IO_BASE1+0x08000000)
#define PA_SPI_BASE           (0x59000000)
#define VA_SPI_BASE           (VA_IO_BASE1+0x09000000)
#define PA_SD_BASE            (0x5A000000)
#define VA_SD_BASE            (VA_IO_BASE1+0x0A000000)



//#define PA_CS8900A_BASE		0x19000000
//#define VA_CS8900A_BASE		0xd0000000

#define PA_CS8900A_BASE       (0x19000000)  /* nGCS3 +0x10000000 */
#define VA_CS8900A_BASE       (VA_IO_BASE2+0x18000000) /* 0xF0000000 */

//#define PA_CS8900A_BASE       (0x19000000)  /* nGCS3 +0x10000000 */
//#define VA_CS8900A_BASE       (0xd0000000) /* 0xF0000000 */


#if LANGUAGE == C

// Memory control 
#define rBWSCON    (*(volatile unsigned *)(VA_MEM_CTR_BASE+0x00)) //Bus width & wait status
#define rBANKCON0  (*(volatile unsigned *)(VA_MEM_CTR_BASE+0x04)) //Boot ROM control
#define rBANKCON1  (*(volatile unsigned *)(VA_MEM_CTR_BASE+0x08)) //BANK1 control
#define rBANKCON2  (*(volatile unsigned *)(VA_MEM_CTR_BASE+0x0c)) //BANK2 cControl
#define rBANKCON3  (*(volatile unsigned *)(VA_MEM_CTR_BASE+0x10)) //BANK3 control
#define rBANKCON4  (*(volatile unsigned *)(VA_MEM_CTR_BASE+0x14)) //BANK4 control
#define rBANKCON5  (*(volatile unsigned *)(VA_MEM_CTR_BASE+0x18)) //BANK5 control
#define rBANKCON6  (*(volatile unsigned *)(VA_MEM_CTR_BASE+0x1c)) //BANK6 control
#define rBANKCON7  (*(volatile unsigned *)(VA_MEM_CTR_BASE+0x20)) //BANK7 control
#define rREFRESH   (*(volatile unsigned *)(VA_MEM_CTR_BASE+0x24)) //DRAM/SDRAM refresh
#define rBANKSIZE  (*(volatile unsigned *)(VA_MEM_CTR_BASE+0x28)) //Flexible Bank Size
#define rMRSRB6    (*(volatile unsigned *)(VA_MEM_CTR_BASE+0x2c)) //Mode register set for SDRAM
#define rMRSRB7    (*(volatile unsigned *)(VA_MEM_CTR_BASE+0x30)) //Mode register set for SDRAM


// USB Host


// INTERRUPT
#define rSRCPND     (*(volatile unsigned *)(VA_INT_BASE+0x00)) //Interrupt request status
#define rINTMOD     (*(volatile unsigned *)(VA_INT_BASE+0x04)) //Interrupt mode control
#define rINTMSK     (*(volatile unsigned *)(VA_INT_BASE+0x08)) //Interrupt mask control
#define rPRIORITY   (*(volatile unsigned *)(VA_INT_BASE+0x0a)) //IRQ priority control
#define rINTPND     (*(volatile unsigned *)(VA_INT_BASE+0x10)) //Interrupt request status
#define rINTOFFSET  (*(volatile unsigned *)(VA_INT_BASE+0x14)) //Interruot request source offset
#define rSUBSRCPND  (*(volatile unsigned *)(VA_INT_BASE+0x18)) //Sub source pending
#define rINTSUBMSK  (*(volatile unsigned *)(VA_INT_BASE+0x1c)) //Interrupt sub mask


// DMA
#define rDISRC0     (*(volatile unsigned *)(VA_DMA_BASE+0x00)) //DMA 0 Initial source
#define rDISRCC0    (*(volatile unsigned *)(VA_DMA_BASE+0x04)) //DMA 0 Initial source control
#define rDIDST0     (*(volatile unsigned *)(VA_DMA_BASE+0x08)) //DMA 0 Initial Destination
#define rDIDSTC0    (*(volatile unsigned *)(VA_DMA_BASE+0x0c)) //DMA 0 Initial Destination control
#define rDCON0      (*(volatile unsigned *)(VA_DMA_BASE+0x10)) //DMA 0 Control
#define rDSTAT0     (*(volatile unsigned *)(VA_DMA_BASE+0x14))//DMA 0 Status
#define rDCSRC0     (*(volatile unsigned *)(VA_DMA_BASE+0x18))//DMA 0 Current source
#define rDCDST0     (*(volatile unsigned *)(VA_DMA_BASE+0x1c))//DMA 0 Current destination
#define rDMASKTRIG0 (*(volatile unsigned *)(VA_DMA_BASE+0x20))//DMA 0 Mask trigger

#define rDISRC1     (*(volatile unsigned *)(VA_DMA_BASE+0x40))//DMA 1 Initial source
#define rDISRCC1    (*(volatile unsigned *)(VA_DMA_BASE+0x44))//DMA 1 Initial source control
#define rDIDST1     (*(volatile unsigned *)(VA_DMA_BASE+0x48))//DMA 1 Initial Destination
#define rDIDSTC1    (*(volatile unsigned *)(VA_DMA_BASE+0x4c))//DMA 1 Initial Destination control
#define rDCON1      (*(volatile unsigned *)(VA_DMA_BASE+0x50))//DMA 1 Control
#define rDSTAT1     (*(volatile unsigned *)(VA_DMA_BASE+0x54))//DMA 1 Status
#define rDCSRC1     (*(volatile unsigned *)(VA_DMA_BASE+0x58))//DMA 1 Current source
#define rDCDST1     (*(volatile unsigned *)(VA_DMA_BASE+0x5c))//DMA 1 Current destination
#define rDMASKTRIG1 (*(volatile unsigned *)(VA_DMA_BASE+0x60))//DMA 1 Mask trigger

#define rDISRC2     (*(volatile unsigned *)(VA_DMA_BASE+0x80))//DMA 2 Initial source
#define rDISRCC2    (*(volatile unsigned *)(VA_DMA_BASE+0x84))//DMA 2 Initial source control
#define rDIDST2     (*(volatile unsigned *)(VA_DMA_BASE+0x88))//DMA 2 Initial Destination
#define rDIDSTC2    (*(volatile unsigned *)(VA_DMA_BASE+0x8c))//DMA 2 Initial Destination control
#define rDCON2      (*(volatile unsigned *)(VA_DMA_BASE+0x90))//DMA 2 Control
#define rDSTAT2     (*(volatile unsigned *)(VA_DMA_BASE+0x94))//DMA 2 Status
#define rDCSRC2     (*(volatile unsigned *)(VA_DMA_BASE+0x98))//DMA 2 Current source
#define rDCDST2     (*(volatile unsigned *)(VA_DMA_BASE+0x9c))//DMA 2 Current destination
#define rDMASKTRIG2 (*(volatile unsigned *)(VA_DMA_BASE+0xa0))//DMA 2 Mask trigger

#define rDISRC3     (*(volatile unsigned *)(VA_DMA_BASE+0xc0))//DMA 3 Initial source
#define rDISRCC3    (*(volatile unsigned *)(VA_DMA_BASE+0xc4))//DMA 3 Initial source control
#define rDIDST3     (*(volatile unsigned *)(VA_DMA_BASE+0xc8))//DMA 3 Initial Destination
#define rDIDSTC3    (*(volatile unsigned *)(VA_DMA_BASE+0xcc))//DMA 3 Initial Destination control
#define rDCON3      (*(volatile unsigned *)(VA_DMA_BASE+0xd0))//DMA 3 Control
#define rDSTAT3     (*(volatile unsigned *)(VA_DMA_BASE+0xd4))//DMA 3 Status
#define rDCSRC3     (*(volatile unsigned *)(VA_DMA_BASE+0xd8))//DMA 3 Current source
#define rDCDST3     (*(volatile unsigned *)(VA_DMA_BASE+0xdc))//DMA 3 Current destination
#define rDMASKTRIG3 (*(volatile unsigned *)(VA_DMA_BASE+0xe0))//DMA 3 Mask trigger

/* DMA Device Address Reg. channel [0..3] */
#define DMASp   	0x40	  /* DMA control reg. Space [byte]   */
#define ARRAY_DISRC(Nb)	((volatile unsigned *)(VA_DMA_BASE+(Nb)*DMASp))
 /*  USED  s3c2410_init_dma functions in arch/arm/mach-s3c2410/dma-s3c2410.c  */

/* 
   STAT 00 = it indicates DMA controller ready
        01 =              DMA controller BUSY 
*/
#define DSTAT_STAT_READY      0x000000         
#define DSTAT_STAT_BUSY       0x100000         

#define DMASKTRIG_STOP        0x4 /* 0100 */
#define DMASKTRIG_START       0x0 /*  */
#define DMASKTRIG_ON          0x2
#define DMASKTRIG_OFF         0x0
#define DMASKTRIG_NO_SW_TRIG     0x0

/* DMA CONTROL REGISTER FlAG */
#define DCON_HS_MODE        ( 0x1 << 30)
#define DCON_SYNC_AHB       ( 0x1 << 29)
#define DCON_INT_ENABLE     ( 0x1 << 28)
#define DCON_TSZ_BURST      ( 0x1 << 27)
#define DCON_WHSR_MODE      ( 0x1 << 26)
#define DCON_HWSRCSEL_I2SDO ( 0x00 << 24)
#define DCON_HW_SEL         ( 0x1 << 23)
#define DCON_NO_AUTO_RELOAD ( 0x1 << 22)
#define DCON_DSZ_HWORD      ( 0x1 << 20)




// CLOCK & POWER MANAGEMENT
#define rLOCKTIME   (*(volatile unsigned *)(VA_CKPO_BASE+0x00))//PLL lock time counter
#define rMPLLCON    (*(volatile unsigned *)(VA_CKPO_BASE+0x04)) //MPLL Control
#define rUPLLCON    (*(volatile unsigned *)(VA_CKPO_BASE+0x08)) //UPLL Control
#define rCLKCON     (*(volatile unsigned *)(VA_CKPO_BASE+0x0c)) //Clock generator control
#define rCLKSLOW    (*(volatile unsigned *)(VA_CKPO_BASE+0x10)) //Slow clock control
#define rCLKDIVN    (*(volatile unsigned *)(VA_CKPO_BASE+0x14)) //Clock divider control


// LCD CONTROLLER
#define LCDCON1    (*(volatile unsigned *)(VA_LCD_BASE+0x00)) //LCD control 1