📄 mc68hc908jb8.h
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byte :1;
byte grpISTALL :1;
byte grpOSTALL :1;
byte :1;
byte :1;
} MergedBits;
} UCR3STR;
extern volatile UCR3STR _UCR3 @0x0000001A;
#define UCR3 _UCR3.Byte
#define UCR3_ENABLE1 _UCR3.Bits.ENABLE1
#define UCR3_ENABLE2 _UCR3.Bits.ENABLE2
#define UCR3_PULLEN _UCR3.Bits.PULLEN
#define UCR3_ISTALL0 _UCR3.Bits.ISTALL0
#define UCR3_OSTALL0 _UCR3.Bits.OSTALL0
#define UCR3_TX1STR _UCR3.Bits.TX1STR
#define UCR3_TX1ST _UCR3.Bits.TX1ST
#define UCR3_ENABLE_1 _UCR3.MergedBits.grpENABLE_1
#define UCR3_ENABLE UCR3_ENABLE_1
#define UCR3_ENABLE1_MASK 1
#define UCR3_ENABLE1_BITNUM 0
#define UCR3_ENABLE2_MASK 2
#define UCR3_ENABLE2_BITNUM 1
#define UCR3_PULLEN_MASK 4
#define UCR3_PULLEN_BITNUM 2
#define UCR3_ISTALL0_MASK 16
#define UCR3_ISTALL0_BITNUM 4
#define UCR3_OSTALL0_MASK 32
#define UCR3_OSTALL0_BITNUM 5
#define UCR3_TX1STR_MASK 64
#define UCR3_TX1STR_BITNUM 6
#define UCR3_TX1ST_MASK 128
#define UCR3_TX1ST_BITNUM 7
#define UCR3_ENABLE_1_MASK 3
#define UCR3_ENABLE_1_BITNUM 0
/*** UCR4 - USB Control Register 4; 0x0000001B ***/
typedef union {
byte Byte;
struct {
byte FDM :1; /* Force D- */
byte FDP :1; /* Force D+ */
byte FUSBO :1; /* Force USB Output */
byte :1;
byte :1;
byte :1;
byte :1;
byte :1;
} Bits;
} UCR4STR;
extern volatile UCR4STR _UCR4 @0x0000001B;
#define UCR4 _UCR4.Byte
#define UCR4_FDM _UCR4.Bits.FDM
#define UCR4_FDP _UCR4.Bits.FDP
#define UCR4_FUSBO _UCR4.Bits.FUSBO
#define UCR4_FDM_MASK 1
#define UCR4_FDM_BITNUM 0
#define UCR4_FDP_MASK 2
#define UCR4_FDP_BITNUM 1
#define UCR4_FUSBO_MASK 4
#define UCR4_FUSBO_BITNUM 2
/*** IOCR - IRQ Option Register; 0x0000001C ***/
typedef union {
byte Byte;
struct {
byte IRQPD :1; /* IRQ Pullup Disable */
byte PTE4IE :1; /* PTE4 Interrupt Enable */
byte PTE4IF :1; /* PTE4 Interrupt Flag */
byte :1;
byte :1;
byte :1;
byte :1;
byte :1;
} Bits;
} IOCRSTR;
extern volatile IOCRSTR _IOCR @0x0000001C;
#define IOCR _IOCR.Byte
#define IOCR_IRQPD _IOCR.Bits.IRQPD
#define IOCR_PTE4IE _IOCR.Bits.PTE4IE
#define IOCR_PTE4IF _IOCR.Bits.PTE4IF
#define IOCR_IRQPD_MASK 1
#define IOCR_IRQPD_BITNUM 0
#define IOCR_PTE4IE_MASK 2
#define IOCR_PTE4IE_BITNUM 1
#define IOCR_PTE4IF_MASK 4
#define IOCR_PTE4IF_BITNUM 2
/*** POCR - Port Option Control Register; 0x0000001D ***/
typedef union {
byte Byte;
struct {
byte PAP :1; /* Port A Pullup Enable */
byte PBP :1; /* Port B Pullup Enable */
byte PCP :1; /* Port C Pullup Enable */
byte PTE3P :1; /* Pin PTE3 Pullup Enable */
byte PTE4P :1; /* Pin PTE4 Pullup Enable */
byte PTDILDD :1; /* Infrared LED Drive Control */
byte PTDLDD :1; /* LED Direct Drive Control */
byte PTE20P :1; /* Pins PTE[2:0] Pullup Enable */
} Bits;
} POCRSTR;
extern volatile POCRSTR _POCR @0x0000001D;
#define POCR _POCR.Byte
#define POCR_PAP _POCR.Bits.PAP
#define POCR_PBP _POCR.Bits.PBP
#define POCR_PCP _POCR.Bits.PCP
#define POCR_PTE3P _POCR.Bits.PTE3P
#define POCR_PTE4P _POCR.Bits.PTE4P
#define POCR_PTDILDD _POCR.Bits.PTDILDD
#define POCR_PTDLDD _POCR.Bits.PTDLDD
#define POCR_PTE20P _POCR.Bits.PTE20P
#define POCR_PAP_MASK 1
#define POCR_PAP_BITNUM 0
#define POCR_PBP_MASK 2
#define POCR_PBP_BITNUM 1
#define POCR_PCP_MASK 4
#define POCR_PCP_BITNUM 2
#define POCR_PTE3P_MASK 8
#define POCR_PTE3P_BITNUM 3
#define POCR_PTE4P_MASK 16
#define POCR_PTE4P_BITNUM 4
#define POCR_PTDILDD_MASK 32
#define POCR_PTDILDD_BITNUM 5
#define POCR_PTDLDD_MASK 64
#define POCR_PTDLDD_BITNUM 6
#define POCR_PTE20P_MASK 128
#define POCR_PTE20P_BITNUM 7
/*** ISCR - IRQ Status and Control Register; 0x0000001E ***/
typedef union {
byte Byte;
struct {
byte MODE :1; /* IRQ Edge/Level Select Bit */
byte IMASK :1; /* IRQ Interrupt Mask Bit */
byte ACK :1; /* IRQ Interrupt Request Acknowledge Bit */
byte IRQF :1; /* IRQ Flag Bit */
byte :1;
byte :1;
byte :1;
byte :1;
} Bits;
} ISCRSTR;
extern volatile ISCRSTR _ISCR @0x0000001E;
#define ISCR _ISCR.Byte
#define ISCR_MODE _ISCR.Bits.MODE
#define ISCR_IMASK _ISCR.Bits.IMASK
#define ISCR_ACK _ISCR.Bits.ACK
#define ISCR_IRQF _ISCR.Bits.IRQF
#define ISCR_MODE_MASK 1
#define ISCR_MODE_BITNUM 0
#define ISCR_IMASK_MASK 2
#define ISCR_IMASK_BITNUM 1
#define ISCR_ACK_MASK 4
#define ISCR_ACK_BITNUM 2
#define ISCR_IRQF_MASK 8
#define ISCR_IRQF_BITNUM 3
/*** CONFIG - Configuration Register; 0x0000001F ***/
typedef union {
byte Byte;
struct {
byte COPD :1; /* COP Disable Bit */
byte STOP :1; /* STOP Instruction Enable Bit */
byte COPRS :1; /* COP Reset Period Selection Bit */
byte SSREC :1; /* Short Stop Recovery Bit */
byte LVID :1; /* Low Voltage Inhibit Disable Bit */
byte URSTD :1; /* USB Reset Disable Bit */
byte :1;
byte :1;
} Bits;
} CONFIGSTR;
extern volatile CONFIGSTR _CONFIG @0x0000001F;
#define CONFIG _CONFIG.Byte
#define CONFIG_COPD _CONFIG.Bits.COPD
#define CONFIG_STOP _CONFIG.Bits.STOP
#define CONFIG_COPRS _CONFIG.Bits.COPRS
#define CONFIG_SSREC _CONFIG.Bits.SSREC
#define CONFIG_LVID _CONFIG.Bits.LVID
#define CONFIG_URSTD _CONFIG.Bits.URSTD
#define CONFIG_COPD_MASK 1
#define CONFIG_COPD_BITNUM 0
#define CONFIG_STOP_MASK 2
#define CONFIG_STOP_BITNUM 1
#define CONFIG_COPRS_MASK 4
#define CONFIG_COPRS_BITNUM 2
#define CONFIG_SSREC_MASK 8
#define CONFIG_SSREC_BITNUM 3
#define CONFIG_LVID_MASK 16
#define CONFIG_LVID_BITNUM 4
#define CONFIG_URSTD_MASK 32
#define CONFIG_URSTD_BITNUM 5
/*** UE0D0 - USB Endpoint 0 Data Register 0; 0x00000020 ***/
typedef union {
byte Byte;
struct {
byte UE0R00_UE0T00 :1; /* Endpoint 0 Receive Data Buffer 0 Bit 0, Endpoint 0 Transmit Data Buffer 0 Bit 0 */
byte UE0R01_UE0T01 :1; /* Endpoint 0 Receive Data Buffer 0 Bit 1, Endpoint 0 Transmit Data Buffer 0 Bit 1 */
byte UE0R02_UE0T02 :1; /* Endpoint 0 Receive Data Buffer 0 Bit 2, Endpoint 0 Transmit Data Buffer 0 Bit 2 */
byte UE0R03_UE0T03 :1; /* Endpoint 0 Receive Data Buffer 0 Bit 3, Endpoint 0 Transmit Data Buffer 0 Bit 3 */
byte UE0R04_UE0T04 :1; /* Endpoint 0 Receive Data Buffer 0 Bit 4, Endpoint 0 Transmit Data Buffer 0 Bit 4 */
byte UE0R05_UE0T05 :1; /* Endpoint 0 Receive Data Buffer 0 Bit 5, Endpoint 0 Transmit Data Buffer 0 Bit 5 */
byte UE0R06_UE0T06 :1; /* Endpoint 0 Receive Data Buffer 0 Bit 6, Endpoint 0 Transmit Data Buffer 0 Bit 6 */
byte UE0R07_UE0T07 :1; /* Endpoint 0 Receive Data Buffer 0 Bit 7, Endpoint 0 Transmit Data Buffer 0 Bit 7 */
} Bits;
} UE0D0STR;
extern volatile UE0D0STR _UE0D0 @0x00000020;
#define UE0D0 _UE0D0.Byte
#define UE0D0_UE0R00_UE0T00 _UE0D0.Bits.UE0R00_UE0T00
#define UE0D0_UE0R01_UE0T01 _UE0D0.Bits.UE0R01_UE0T01
#define UE0D0_UE0R02_UE0T02 _UE0D0.Bits.UE0R02_UE0T02
#define UE0D0_UE0R03_UE0T03 _UE0D0.Bits.UE0R03_UE0T03
#define UE0D0_UE0R04_UE0T04 _UE0D0.Bits.UE0R04_UE0T04
#define UE0D0_UE0R05_UE0T05 _UE0D0.Bits.UE0R05_UE0T05
#define UE0D0_UE0R06_UE0T06 _UE0D0.Bits.UE0R06_UE0T06
#define UE0D0_UE0R07_UE0T07 _UE0D0.Bits.UE0R07_UE0T07
#define UE0D0_UE0R00_UE0T00_MASK 1
#define UE0D0_UE0R00_UE0T00_BITNUM 0
#define UE0D0_UE0R01_UE0T01_MASK 2
#define UE0D0_UE0R01_UE0T01_BITNUM 1
#define UE0D0_UE0R02_UE0T02_MASK 4
#define UE0D0_UE0R02_UE0T02_BITNUM 2
#define UE0D0_UE0R03_UE0T03_MASK 8
#define UE0D0_UE0R03_UE0T03_BITNUM 3
#define UE0D0_UE0R04_UE0T04_MASK 16
#define UE0D0_UE0R04_UE0T04_BITNUM 4
#define UE0D0_UE0R05_UE0T05_MASK 32
#define UE0D0_UE0R05_UE0T05_BITNUM 5
#define UE0D0_UE0R06_UE0T06_MASK 64
#define UE0D0_UE0R06_UE0T06_BITNUM 6
#define UE0D0_UE0R07_UE0T07_MASK 128
#define UE0D0_UE0R07_UE0T07_BITNUM 7
/*** UE0D1 - USB Endpoint 0 Data Register 1; 0x00000021 ***/
typedef union {
byte Byte;
struct {
byte UE0R10_UE0T10 :1; /* Endpoint 0 Receive Data Buffer 1 Bit 0, Endpoint 0 Transmit Data Buffer 1 Bit 0 */
byte UE0R11_UE0T11 :1; /* Endpoint 0 Receive Data Buffer 1 Bit 1, Endpoint 0 Transmit Data Buffer 1 Bit 1 */
byte UE0R12_UE0T12 :1; /* Endpoint 0 Receive Data Buffer 1 Bit 2, Endpoint 0 Transmit Data Buffer 1 Bit 2 */
byte UE0R13_UE0T13 :1; /* Endpoint 0 Receive Data Buffer 1 Bit 3, Endpoint 0 Transmit Data Buffer 1 Bit 3 */
byte UE0R14_UE0T14 :1; /* Endpoint 0 Receive Data Buffer 1 Bit 4, Endpoint 0 Transmit Data Buffer 1 Bit 4 */
byte UE0R15_UE0T15 :1; /* Endpoint 0 Receive Data Buffer 1 Bit 5, Endpoint 0 Transmit Data Buffer 1 Bit 5 */
byte UE0R16_UE0T16 :1; /* Endpoint 0 Receive Data Buffer 1 Bit 6, Endpoint 0 Transmit Data Buffer 1 Bit 6 */
byte UE0R17_UE0T17 :1; /* Endpoint 0 Receive Data Buffer 1 Bit 7, Endpoint 0 Transmit Data Buffer 1 Bit 7 */
} Bits;
} UE0D1STR;
extern volatile UE0D1STR _UE0D1 @0x00000021;
#define UE0D1 _UE0D1.Byte
#define UE0D1_UE0R10_UE0T10 _UE0D1.Bits.UE0R10_UE0T10
#define UE0D1_UE0R11_UE0T11 _UE0D1.Bits.UE0R11_UE0T11
#define UE0D1_UE0R12_UE0T12 _UE0D1.Bits.UE0R12_UE0T12
#define UE0D1_UE0R13_UE0T13 _UE0D1.Bits.UE0R13_UE0T13
#define UE0D1_UE0R14_UE0T14 _UE0D1.Bits.UE0R14_UE0T14
#define UE0D1_UE0R15_UE0T15 _UE0D1.Bits.UE0R15_UE0T15
#define UE0D1_UE0R16_UE0T16 _UE0D1.Bits.UE0R16_UE0T16
#define UE0D1_UE0R17_UE0T17 _UE0D1.Bits.UE0R17_UE0T17
#define UE0D1_UE0R10_UE0T10_MASK 1
#define UE0D1_UE0R10_UE0T10_BITNUM 0
#define UE0D1_UE0R11_UE0T11_MASK 2
#define UE0D1_UE0R11_UE0T11_BITNUM 1
#define UE0D1_UE0R12_UE0T12_MASK 4
#define UE0D1_UE0R12_UE0T12_BITNUM 2
#define UE0D1_UE0R13_UE0T13_MASK 8
#define UE0D1_UE0R13_UE0T13_BITNUM 3
#define UE0D1_UE0R14_UE0T14_MASK 16
#define UE0D1_UE0R14_UE0T14_BITNUM 4
#define UE0D1_UE0R15_UE0T15_MASK 32
#define UE0D1_UE0R15_UE0T15_BITNUM 5
#define UE0D1_UE0R16_UE0T16_MASK 64
#define UE0D1_UE0R16_UE0T16_BITNUM 6
#define UE0D1_UE0R17_UE0T17_MASK 128
#define UE0D1_UE0R17_UE0T17_BITNUM 7
/*** UE0D2 - USB Endpoint 0 Data Register 2; 0x00000022 ***/
typedef union {
byte Byte;
struct {
byte UE0R20_UE0T20 :1; /* Endpoint 0 Receive Data Buffer 2 Bit 0, Endpoint 0 Transmit Data Buffer 2 Bit 0 */
byte UE0R21_UE0T21 :1; /* Endpoint 0 Receive Data Buffer 2 Bit 1, Endpoint 0 Transmit Data Buffer 2 Bit 1 */
byte UE0R22_UE0T22 :1; /* Endpoint 0 Receive Data Buffer 2 Bit 2, Endpoint 0 Transmit Data Buffer 2 Bit 2 */
byte UE0R23_UE0T23 :1; /* Endpoint 0 Receive Data Buffer 2 Bit 3, Endpoint 0 Transmit Data Buffer 2 Bit 3 */
byte UE0R24_UE0T24 :1; /* Endpoint 0 Receive Data Buffer 2 Bit 4, Endpoint 0 Transmit Data Buffer 2 Bit 4 */
byte UE0R25_UE0T25 :1; /* Endpoint 0 Receive Data Buffer 2 Bit 5, Endpoint 0 Transmit Data Buffer 2 Bit 5 */
byte UE0R26_UE0T26 :1; /* Endpoint 0 Receive Data Buffer 2 Bit 6, Endpoint 0 Transmit Data Buffer 2 Bit 6 */
byte UE0R27_UE0T27 :1; /* Endpoint 0 Receive Data Buffer 2 Bit 7, Endpoint 0 Transmit Data Buffer 2 Bit 7 */
} Bits;
} UE0D2STR;
extern volatile UE0D2STR _UE0D2 @0x00000022;
#define UE0D2 _UE0D2.Byte
#define UE0D2_UE0R20_UE0T20 _UE0D2.Bits.UE0R20_UE0T20
#define UE0D2_UE0R21_UE0T21 _UE0D2.Bits.UE0R21_UE0T21
#define UE0D2_UE0R22_UE0T22 _UE0D2.Bits.UE0R22_UE0T22
#define UE0D2_UE0R23_UE0T23 _UE0D2.Bits.UE0R23_UE0T23
#define UE0D2_UE0R24_UE0T24 _UE0D2.Bits.UE0R24_UE0T24
#define UE0D2_UE0R25_UE0T25 _UE0D2.Bits.UE0R25_UE0T25
#define UE0D2_UE0R26_UE0T26 _UE0D2.Bits.UE0R26_UE0T26
#define UE0D2_UE0R27_UE0T27 _UE0D2.Bits.UE0R27_UE0T27
#define UE0D2_UE0R20_UE0T20_MASK 1
#define UE0D2_UE0R20_UE0T20_BITNUM 0
#define UE0D2_UE0R21_UE0T21_MASK 2
#define UE0D2_UE0R21_UE0T21_BITNUM 1
#define UE0D2_UE0R22_UE0T22_MASK 4
#define UE0D2_UE0R22_UE0T22_BITNUM 2
#define UE0D2_UE0R23_UE0T23_MASK 8
#define UE0D2_UE0R23_UE0T23_BITNUM 3
#define UE0D2_UE0R24_UE0T24_MASK 16
#define UE0D2_UE0R24_UE0T24_BITNUM 4
#define UE0D2_UE0R25_UE0T25_MASK 32
#define UE0D2_UE0R25_UE0T25_BITNUM 5
#define UE0D2_UE0R26_UE0T26_MASK 64
#define UE0D2_UE0R26_UE0T26_BITNUM 6
#define UE0D2_UE0R27_UE0T27_MASK⌨️ 快捷键说明
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