bdm.h

Freescale的S08BDM开发工具制作资料

#define BUS_FREQUENCY 6     /* JB8 runs at 3 MHz */
#define ACKN_TIMEOUT  375   /* longest time after which the target should produce ACKN pulse (150 cycles @ 400kHz = 375us) */
#define BDM_SYNC_REQ  350   /* length of the longest possible SYNC REQUEST pulse (128 BDM cycles @ 400kHz = 320us plus some extra time) */
#define SOFT_RESET    1280  /* longest time needed for soft reset of the BDM interface (512 BDM cycles @ 400kHz = 1280us) */
#define RESET_WAIT    300   /* how long to wait for the reset pin to come high in *ms* */
#define RESET_SETTLE  3000  /* time to wait for signals to settle in us, this should certainly be longer than the soft reset time */
#define RESET_LENGTH  100   /* time of RESET assertion in *ms* */

/* please note: pin assignements cannot be changed freely */
/* RX AND TX ROUTINES ARE DEPENDANT ON THIS SPECIFIC ASSIGNEMENT */
#define BDM_IN        PTA_PTA6
#define BDM_IN_MASK   PTA_PTA6_MASK
#define BDM_IN_PORT   PTA
#define BDM_IN_DDR    DDRA

#define BDM_OUT       PTA_PTA7
#define BDM_OUT_MASK  PTA_PTA7_MASK
#define BDM_OUT_PORT  PTA
#define BDM_OUT_DDR   DDRA

#define BDM_DIR1      PTA_PTA4
#define BDM_DIR1_MASK PTA_PTA4_MASK
#define BDM_DIR1_PORT PTA
#define BDM_DIR1_DDR  DDRA

#define BDM_DIR2      PTC_PTC0
#define BDM_DIR2_MASK PTC_PTC0_MASK
#define BDM_DIR2_PORT PTC
#define BDM_DIR2_DDR  DDRC

#define RESET_DR      PTC_PTC1
#define RESET_DR_MASK PTC_PTC1_MASK
#define RESET_DR_PORT PTC
#define RESET_DR_DDR  DDRC


#define RESET_OUT      PTA_PTA1
#define RESET_OUT_MASK PTA_PTA1_MASK
#define RESET_OUT_PORT PTA
#define RESET_OUT_DDR  DDRA

#define RESET_IN      PTA_PTA5
#define RESET_IN_MASK PTA_PTA5_MASK
#define RESET_IN_PORT PTA
#define RESET_IN_DDR  DDRA

void bdm_init(void);
unsigned char bdm_rx1(void);
unsigned char bdm_rx2(void);
unsigned char bdm_rx3(void);
unsigned char bdm_rx4(void);
unsigned char bdm_rx5(void);
unsigned char bdm_rx6(void);
unsigned char bdm_rx7(void);
unsigned char bdm_rx8(void);
unsigned char bdm_rx9(void);
unsigned char bdm_rx10(void);
unsigned char bdm_rx11(void);
unsigned char bdm_rx12(void);
unsigned char bdm_rx13(void);
unsigned char bdm_rx14(void);
unsigned char bdm_rx15(void);
void bdm_tx1(unsigned char data);
void bdm_tx2(unsigned char data);
void bdm_tx3(unsigned char data);
void bdm_tx4(unsigned char data);
void bdm_tx5(unsigned char data);
void bdm_tx6(unsigned char data);
void bdm_tx7(unsigned char data);
void bdm_tx8(unsigned char data);
void bdm_tx9(unsigned char data);
void bdm_tx10(unsigned char data);
void bdm_tx11(unsigned char data);
void bdm_tx12(unsigned char data);
void bdm_tx13(unsigned char data);
void bdm_tx14(unsigned char data);
void bdm_tx15(unsigned char data);
void bdm_tx16(unsigned char data);
void bdm_tx17(unsigned char data);
void bdm_tx18(unsigned char data);
void bdm_tx19(unsigned char data);
unsigned char bdm_empty_rx_tx(void);
unsigned char bdm_rx_tx_select(void);
void bdm_tx_prepare(void);
void rx_stack_decode(void);
void bdm_tx_finish(void);
void bdm_ackn(void);
void bdm_wait64(void);
void bdm_wait150(void);
void bdm_ackn_init(void);
unsigned char bdm_sync_meas(void);
unsigned char bdm_reset(unsigned char mode); 
unsigned char bdm_softreset(unsigned char mode); 
unsigned char bdm08_stat(void);

unsigned char bdm12_connect(void);
unsigned char bdm08_connect(void); 
typedef enum {
  HC12=0,
  HCS08=1
} target_type_e;

typedef enum {
  WAIT=0,                 /* use WAIT instead */
  ACKN=1									/* ACKN feature available and enabled */
} ackn_e;

typedef enum {
  NO_RESET_ACTIVITY=0,
  RESET_DETECTED=1
} reset_e;

typedef enum {
  NO_INFO=0,
  SYNC_SUPPORTED=1,
  SPEED_GUESSED=2,
  SPEED_USER_SUPPLIED=3
} speed_e;

typedef struct {
  unsigned char target_type:2;  /*  target_type_e */
  unsigned char ackn:1;         /*  ackn_e */
  unsigned char reset:1;        /*  reset_e */
  unsigned char speed:2;			  /*  speed_e */
  unsigned char wait150_cnt;    /* time of 150 BDM cycles in bus cycles of the MCU divided by 3 */
  unsigned char wait64_cnt;  
  unsigned int sync_length;     /* length of the target SYNC pulse in 60MHz ticks */
} bdm_status_t;

extern bdm_status_t bdm_status;
extern unsigned char (*bdm_rx_ptr)(void);
extern void (*bdm_tx_ptr)(unsigned char);

#define bdm_rx()      (*bdm_rx_ptr)() 
#define bdm_tx(data)  (*bdm_tx_ptr)(data) 

/* hardware commands */
#define _BDM_BACKGROUND		    0x90
#define _BDM_ACK_ENABLE		    0xD5
#define _BDM_ACK_DISABLE	    0xD6
#define _BDM_READ_BYTE		    0xE0
#define _BDM_WRITE_BYTE		    0xC0
/* HC/S12(x) hardware commands */
#define _BDM12_READ_BD_BYTE	  0xE4
#define _BDM12_READ_BD_WORD	  0xEC
#define _BDM12_READ_WORD	    0xE8
#define _BDM12_WRITE_BD_BYTE  0xC4
#define _BDM12_WRITE_BD_WORD  0xCC
#define _BDM12_WRITE_WORD	    0xC8
/* HCS08 'hardware'(non-intrusive) commands */
#define _BDM08_READ_STATUS	  0xE4
#define _BDM08_WRITE_CONTROL  0xC4
#define _BDM08_READ_BYTE_WS	  0xE1
#define _BDM08_READ_LAST	    0xE8
#define _BDM08_WRITE_BYTE_WS  0xC1
#define _BDM08_READ_BKPT	    0xE2
#define _BDM08_WRITE_BKPT     0xC2

/* firmware commands */
#define _BDM_GO				        0x08
#define _BDM_TRACE1           0x10
#define _BDM_TAGGO			      0x18

/* HCS08 'firmware' (active background mode) commands */
#define _BDM08_READ_A		      0x68
#define _BDM08_READ_CCR		    0x69
#define _BDM08_READ_PC		    0x6B
#define _BDM08_READ_HX		    0x6C
#define _BDM08_READ_SP		    0x6F
#define _BDM08_READ_NEXT	    0x70
#define _BDM08_READ_NEXT_WS	  0x71
#define _BDM08_WRITE_A		    0x48
#define _BDM08_WRITE_CCR	    0x49
#define _BDM08_WRITE_PC		    0x4B
#define _BDM08_WRITE_HX		    0x4C
#define _BDM08_WRITE_SP	    	0x4F
#define _BDM08_WRITE_NEXT		  0x50
#define _BDM08_NEXT_WS		    0x51


/* HC/S12(x) firmware commands */
#define _BDM12_READ_NEXT	    0x62
#define _BDM12_READ_PC		    0x63
#define _BDM12_READ_D		      0x64
#define _BDM12_READ_X		      0x65
#define _BDM12_READ_Y		      0x66
#define _BDM12_READ_SP		    0x67
#define _BDM12_WRITE_NEXT	    0x42
#define _BDM12_WRITE_PC		    0x43
#define _BDM12_WRITE_D		    0x44
#define _BDM12_WRITE_X		    0x45