📄 alu.vhd
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-- alu.vhd
-- This module implements a 16-bit ALU
-- Inputs:
-- A, B - 16-bit inputs
-- ALUop - 4-bit Select for ALU operation
-- Outputs:
-- Result - 16-bit result output
-- Zero - 1-bit zero result output
-- Author: Easyright
-- E-mail: support@easyright.net
-- Date: 17-08-2003
-- Copyright: http://www.EasyRight.net
------------------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity alu is
port (
A, B: in std_logic_vector(15 downto 0);
ALUop: in std_logic_vector(3 downto 0);
Result: out std_logic_vector(15 downto 0);
Zero: out std_logic
);
end alu;
architecture arc_alu of alu is
Signal res: std_logic_vector(15 downto 0);
function btobv(b: boolean) return bit_vector is
begin
if b then
return "0000000000000001";
else
return "0000000000000000";
end if;
end function btobv;
begin
with ALUop select
res <= A + B when "0011",
A + (not B) + 1 when "0001",
not A when "0111",
A and B when "0000",
A or B when "0010",
To_StdLogicVector(To_bitvector(A, '0') srl CONV_INTEGER(B+B)) when "0100",
To_StdLogicVector(To_bitvector(A, '0') sra CONV_INTEGER(B+B)) when "0101",
To_StdLogicVector(To_bitvector(A, '0') sla CONV_INTEGER(B+B)) when "0110",
To_StdLogicVector(btobv(A < B)) when "1100",
To_StdLogicVector(btobv(A > B)) when "1001",
To_StdLogicVector(btobv(A <= B)) when "1110",
To_StdLogicVector(btobv(A >= B)) when "1011",
To_StdLogicVector(btobv(A = B)) when "1010",
To_StdLogicVector(btobv(A /= B)) when "1101",
"0000000000000000" when others;
Result <= res;
Zero <= not(res(0) or res(1) or res(2) or res(3) or res(4) or res(5) or res(6) or res(7) or
res(8) or res(9) or res(10) or res(11) or res(12) or res(13) or res(14) or res(15));
end arc_alu;
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