📄 aluctrl.vhd
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-- aluctrl.vhd
-- This circuit generates control signal for the ALU so that ALU can execute
-- different operations.
-- Inputs:
-- ALUop - 4-bit Select for ALU operation
-- Func - 3-bit Select for ALU operation
-- Outputs:
-- ALUcs - 4-bit control signal for ALU
-- Author: Easyright
-- E-mail: support@easyright.net
-- Date: 27-08-2003
-- Copyright: http://www.EasyRight.net
------------------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity aluctrl is
port (
ALUop: in std_logic_vector(3 downto 0);
Func: in std_logic_vector(2 downto 0);
ALUcs: out std_logic_vector(3 downto 0)
);
end aluctrl;
architecture arc_aluctrl of aluctrl is
begin
process(ALUop, Func)
begin
if (ALUop(3)='1' and ALUop(2)='0') then -- beqz
ALUcs <= "0001";
elsif (ALUop(3)='1' and ALUop(2)='1') then -- lw, sw
ALUcs <= "0011";
elsif ALUop(3)='0' then -- test and arithmetic
ALUcs(3) <= not ALUop(0);
ALUcs(2) <= Func(2);
ALUcs(1) <= Func(1);
ALUcs(0) <= Func(0);
end if;
end process;
end arc_aluctrl;
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