📄 pems800v05.acf
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VERILOG_NETLIST_WRITER = OFF;
VHDL_NETLIST_WRITER = OFF;
USE_SYNOPSYS_SYNTHESIS = OFF;
SYNOPSYS_COMPILER = DESIGN;
SYNOPSYS_DESIGNWARE = OFF;
SYNOPSYS_HIERARCHICAL_COMPILATION = ON;
SYNOPSYS_BOUNDARY_OPTIMIZATION = OFF;
SYNOPSYS_MAPPING_EFFORT = MEDIUM;
VHDL_READER_VERSION = VHDL87;
VHDL_WRITER_VERSION = VHDL87;
USE_ADT_PALACE_FOR_MAX = OFF;
END;
CUSTOM_DESIGN_DOCTOR_RULES
BEGIN
RIPPLE_CLOCKS = ON;
GATED_CLOCKS = ON;
MULTI_LEVEL_CLOCKS = ON;
MULTI_CLOCK_NETWORKS = ON;
STATIC_HAZARDS_BEFORE_SYNTHESIS = ON;
STATIC_HAZARDS_AFTER_SYNTHESIS = OFF;
PRESET_CLEAR_NETWORKS = ON;
ASYNCHRONOUS_INPUTS = ON;
DELAY_CHAINS = ON;
RACE_CONDITIONS = ON;
EXPANDER_NETWORKS = ON;
MASTER_RESET = OFF;
END;
SIMULATOR_CONFIGURATION
BEGIN
USE_DEVICE = OFF;
SETUP_HOLD = OFF;
CHECK_OUTPUTS = OFF;
OSCILLATION = OFF;
OSCILLATION_TIME = 0.0ns;
GLITCH = OFF;
GLITCH_TIME = 0.0ns;
START_TIME = 0.0ns;
END_TIME = 0.0ns;
BIDIR_PIN = STRONG;
END;
TIMING_ANALYZER_CONFIGURATION
BEGIN
ANALYSIS_MODE = DELAY_MATRIX;
AUTO_RECALCULATE = OFF;
CUT_OFF_IO_PIN_FEEDBACK = ON;
CUT_OFF_CLEAR_AND_PRESET_PATHS = ON;
LIST_ONLY_LONGEST_PATH = ON;
CELL_WIDTH = 18;
DELAY_MATRIX_OPTIONS = SHOW_ALL_PATHS;
INCLUDE_PATHS_GREATER_THAN = OFF;
INCLUDE_PATHS_GREATER_THAN_VALUE = 0.0ns;
INCLUDE_PATHS_LESS_THAN = OFF;
INCLUDE_PATHS_LESS_THAN_VALUE = 214.7483647ms;
REGISTERED_PERFORMANCE_OPTIONS = NUMBER_OF_PATHS;
LIST_PATH_COUNT = 10;
LIST_PATH_FREQUENCY = 10MHz;
CUT_OFF_RAM_REGISTERED_WE_PATHS = OFF;
END;
OTHER_CONFIGURATION
BEGIN
EXPLICIT_FAMILY = 1;
COMPILER_DATA = "1,1,0,1,0,0,0,1,1,1,1,0,1,1,1";
ORIGINAL_MAXPLUS2_VERSION = 9.21;
ROW_PINS_PERCENT = 50;
EXP_PER_LCELL_PERCENT = 100;
FAN_IN_PER_LCELL_PERCENT = 100;
LCELLS_PER_ROW_PERCENT = 100;
LOCAL_INTERCONNECT_PER_LAB_PERCENT = 100;
DEFAULT_9K_EXP_PER_LCELL = 1/2;
FLEX_10K_52_COLUMNS = 40;
LAST_MAXPLUS2_VERSION = 10.2;
END;
DEFINE_LOGIC_SYNTHESIS_STYLE NORMAL.MAX5000
BEGIN
CASCADE_CHAIN = IGNORE;
CASCADE_CHAIN_LENGTH = -1;
CARRY_CHAIN = IGNORE;
CARRY_CHAIN_LENGTH = -1;
MINIMIZATION = FULL;
SLOW_SLEW_RATE = OFF;
XOR_SYNTHESIS = ON;
TURBO_BIT = OFF;
PARALLEL_EXPANDERS = OFF;
IGNORE_SOFT_BUFFERS = OFF;
FAST_IO = OFF;
SOFT_BUFFER_INSERTION = ON;
DECOMPOSE_GATES = ON;
REDUCE_LOGIC = ON;
DUPLICATE_LOGIC_EXTRACTION = ON;
NOT_GATE_PUSH_BACK = ON;
REFACTORIZATION = ON;
SUBFACTOR_EXTRACTION = ON;
MULTI_LEVEL_FACTORING = ON;
RESYNTHESIZE_NETWORK = ON;
USE_LPM_FOR_AHDL_OPERATORS = OFF;
REGISTER_OPTIMIZATION = ON;
END;
DEFINE_LOGIC_SYNTHESIS_STYLE NORMAL.MAX7000
BEGIN
CASCADE_CHAIN = IGNORE;
CASCADE_CHAIN_LENGTH = -1;
CARRY_CHAIN = IGNORE;
CARRY_CHAIN_LENGTH = -1;
MINIMIZATION = FULL;
SLOW_SLEW_RATE = OFF;
XOR_SYNTHESIS = ON;
TURBO_BIT = ON;
PARALLEL_EXPANDERS = OFF;
IGNORE_SOFT_BUFFERS = OFF;
FAST_IO = OFF;
SOFT_BUFFER_INSERTION = ON;
DECOMPOSE_GATES = ON;
REDUCE_LOGIC = ON;
DUPLICATE_LOGIC_EXTRACTION = ON;
NOT_GATE_PUSH_BACK = ON;
REFACTORIZATION = ON;
SUBFACTOR_EXTRACTION = ON;
MULTI_LEVEL_FACTORING = ON;
RESYNTHESIZE_NETWORK = ON;
USE_LPM_FOR_AHDL_OPERATORS = OFF;
REGISTER_OPTIMIZATION = ON;
END;
DEFINE_LOGIC_SYNTHESIS_STYLE NORMAL.CLASSIC
BEGIN
CASCADE_CHAIN = IGNORE;
CASCADE_CHAIN_LENGTH = -1;
CARRY_CHAIN = IGNORE;
CARRY_CHAIN_LENGTH = -1;
MINIMIZATION = FULL;
SLOW_SLEW_RATE = OFF;
XOR_SYNTHESIS = OFF;
TURBO_BIT = ON;
PARALLEL_EXPANDERS = OFF;
IGNORE_SOFT_BUFFERS = OFF;
FAST_IO = OFF;
SOFT_BUFFER_INSERTION = ON;
DECOMPOSE_GATES = ON;
REDUCE_LOGIC = OFF;
DUPLICATE_LOGIC_EXTRACTION = OFF;
NOT_GATE_PUSH_BACK = ON;
REFACTORIZATION = OFF;
SUBFACTOR_EXTRACTION = OFF;
MULTI_LEVEL_FACTORING = OFF;
RESYNTHESIZE_NETWORK = ON;
USE_LPM_FOR_AHDL_OPERATORS = OFF;
REGISTER_OPTIMIZATION = OFF;
END;
DEFINE_LOGIC_SYNTHESIS_STYLE NORMAL.FLEX8000
BEGIN
CASCADE_CHAIN = IGNORE;
CASCADE_CHAIN_LENGTH = 2;
CARRY_CHAIN = IGNORE;
CARRY_CHAIN_LENGTH = 32;
MINIMIZATION = FULL;
SLOW_SLEW_RATE = OFF;
XOR_SYNTHESIS = OFF;
TURBO_BIT = OFF;
PARALLEL_EXPANDERS = OFF;
IGNORE_SOFT_BUFFERS = ON;
SOFT_BUFFER_INSERTION = ON;
DECOMPOSE_GATES = ON;
REDUCE_LOGIC = ON;
DUPLICATE_LOGIC_EXTRACTION = ON;
NOT_GATE_PUSH_BACK = ON;
REFACTORIZATION = ON;
SUBFACTOR_EXTRACTION = ON;
MULTI_LEVEL_FACTORING = ON;
RESYNTHESIZE_NETWORK = ON;
USE_LPM_FOR_AHDL_OPERATORS = OFF;
REGISTER_OPTIMIZATION = ON;
END;
DEFINE_LOGIC_SYNTHESIS_STYLE FAST.MAX5000
BEGIN
CASCADE_CHAIN = IGNORE;
CASCADE_CHAIN_LENGTH = -1;
CARRY_CHAIN = IGNORE;
CARRY_CHAIN_LENGTH = -1;
MINIMIZATION = FULL;
SLOW_SLEW_RATE = OFF;
XOR_SYNTHESIS = ON;
TURBO_BIT = OFF;
PARALLEL_EXPANDERS = OFF;
IGNORE_SOFT_BUFFERS = OFF;
FAST_IO = OFF;
SOFT_BUFFER_INSERTION = ON;
DECOMPOSE_GATES = ON;
REDUCE_LOGIC = ON;
DUPLICATE_LOGIC_EXTRACTION = ON;
NOT_GATE_PUSH_BACK = ON;
REFACTORIZATION = OFF;
SUBFACTOR_EXTRACTION = OFF;
MULTI_LEVEL_FACTORING = ON;
RESYNTHESIZE_NETWORK = ON;
USE_LPM_FOR_AHDL_OPERATORS = OFF;
REGISTER_OPTIMIZATION = ON;
END;
DEFINE_LOGIC_SYNTHESIS_STYLE FAST.MAX7000
BEGIN
CASCADE_CHAIN = IGNORE;
CASCADE_CHAIN_LENGTH = -1;
CARRY_CHAIN = IGNORE;
CARRY_CHAIN_LENGTH = -1;
MINIMIZATION = FULL;
SLOW_SLEW_RATE = OFF;
XOR_SYNTHESIS = ON;
TURBO_BIT = ON;
PARALLEL_EXPANDERS = ON;
IGNORE_SOFT_BUFFERS = OFF;
FAST_IO = OFF;
SOFT_BUFFER_INSERTION = ON;
DECOMPOSE_GATES = ON;
REDUCE_LOGIC = ON;
DUPLICATE_LOGIC_EXTRACTION = ON;
NOT_GATE_PUSH_BACK = ON;
REFACTORIZATION = OFF;
SUBFACTOR_EXTRACTION = OFF;
MULTI_LEVEL_FACTORING = ON;
RESYNTHESIZE_NETWORK = ON;
USE_LPM_FOR_AHDL_OPERATORS = OFF;
REGISTER_OPTIMIZATION = ON;
END;
DEFINE_LOGIC_SYNTHESIS_STYLE FAST.CLASSIC
BEGIN
CASCADE_CHAIN = IGNORE;
CASCADE_CHAIN_LENGTH = -1;
CARRY_CHAIN = IGNORE;
CARRY_CHAIN_LENGTH = -1;
MINIMIZATION = FULL;
SLOW_SLEW_RATE = OFF;
XOR_SYNTHESIS = OFF;
TURBO_BIT = ON;
PARALLEL_EXPANDERS = OFF;
IGNORE_SOFT_BUFFERS = OFF;
FAST_IO = OFF;
SOFT_BUFFER_INSERTION = ON;
DECOMPOSE_GATES = ON;
REDUCE_LOGIC = OFF;
DUPLICATE_LOGIC_EXTRACTION = OFF;
NOT_GATE_PUSH_BACK = ON;
REFACTORIZATION = OFF;
SUBFACTOR_EXTRACTION = OFF;
MULTI_LEVEL_FACTORING = OFF;
RESYNTHESIZE_NETWORK = ON;
USE_LPM_FOR_AHDL_OPERATORS = OFF;
REGISTER_OPTIMIZATION = OFF;
END;
DEFINE_LOGIC_SYNTHESIS_STYLE FAST.FLEX8000
BEGIN
CASCADE_CHAIN = AUTO;
CASCADE_CHAIN_LENGTH = 2;
CARRY_CHAIN = AUTO;
CARRY_CHAIN_LENGTH = 32;
MINIMIZATION = FULL;
SLOW_SLEW_RATE = OFF;
XOR_SYNTHESIS = OFF;
TURBO_BIT = OFF;
PARALLEL_EXPANDERS = OFF;
IGNORE_SOFT_BUFFERS = ON;
SOFT_BUFFER_INSERTION = ON;
DECOMPOSE_GATES = ON;
REDUCE_LOGIC = ON;
DUPLICATE_LOGIC_EXTRACTION = ON;
NOT_GATE_PUSH_BACK = ON;
REFACTORIZATION = OFF;
SUBFACTOR_EXTRACTION = OFF;
MULTI_LEVEL_FACTORING = ON;
RESYNTHESIZE_NETWORK = ON;
USE_LPM_FOR_AHDL_OPERATORS = OFF;
REGISTER_OPTIMIZATION = ON;
END;
DEFINE_LOGIC_SYNTHESIS_STYLE WYSIWYG.MAX5000
BEGIN
CASCADE_CHAIN = IGNORE;
CASCADE_CHAIN_LENGTH = -1;
CARRY_CHAIN = IGNORE;
CARRY_CHAIN_LENGTH = -1;
MINIMIZATION = PARTIAL;
SLOW_SLEW_RATE = OFF;
XOR_SYNTHESIS = OFF;
TURBO_BIT = OFF;
PARALLEL_EXPANDERS = OFF;
IGNORE_SOFT_BUFFERS = OFF;
FAST_IO = OFF;
SOFT_BUFFER_INSERTION = OFF;
DECOMPOSE_GATES = OFF;
REDUCE_LOGIC = OFF;
DUPLICATE_LOGIC_EXTRACTION = OFF;
NOT_GATE_PUSH_BACK = ON;
REFACTORIZATION = OFF;
SUBFACTOR_EXTRACTION = OFF;
MULTI_LEVEL_FACTORING = OFF;
RESYNTHESIZE_NETWORK = OFF;
USE_LPM_FOR_AHDL_OPERATORS = OFF;
REGISTER_OPTIMIZATION = OFF;
END;
DEFINE_LOGIC_SYNTHESIS_STYLE WYSIWYG.MAX7000
BEGIN
CASCADE_CHAIN = IGNORE;
CASCADE_CHAIN_LENGTH = -1;
CARRY_CHAIN = IGNORE;
CARRY_CHAIN_LENGTH = -1;
MINIMIZATION = PARTIAL;
SLOW_SLEW_RATE = OFF;
XOR_SYNTHESIS = OFF;
TURBO_BIT = ON;
PARALLEL_EXPANDERS = OFF;
IGNORE_SOFT_BUFFERS = OFF;
FAST_IO = OFF;
SOFT_BUFFER_INSERTION = OFF;
DECOMPOSE_GATES = OFF;
REDUCE_LOGIC = OFF;
DUPLICATE_LOGIC_EXTRACTION = OFF;
NOT_GATE_PUSH_BACK = ON;
REFACTORIZATION = OFF;
SUBFACTOR_EXTRACTION = OFF;
MULTI_LEVEL_FACTORING = OFF;
RESYNTHESIZE_NETWORK = OFF;
USE_LPM_FOR_AHDL_OPERATORS = OFF;
REGISTER_OPTIMIZATION = OFF;
END;
DEFINE_LOGIC_SYNTHESIS_STYLE WYSIWYG.CLASSIC
BEGIN
CASCADE_CHAIN = IGNORE;
CASCADE_CHAIN_LENGTH = -1;
CARRY_CHAIN = IGNORE;
CARRY_CHAIN_LENGTH = -1;
MINIMIZATION = PARTIAL;
SLOW_SLEW_RATE = OFF;
XOR_SYNTHESIS = OFF;
TURBO_BIT = ON;
PARALLEL_EXPANDERS = OFF;
IGNORE_SOFT_BUFFERS = OFF;
FAST_IO = OFF;
SOFT_BUFFER_INSERTION = OFF;
DECOMPOSE_GATES = ON;
REDUCE_LOGIC = OFF;
DUPLICATE_LOGIC_EXTRACTION = OFF;
NOT_GATE_PUSH_BACK = ON;
REFACTORIZATION = OFF;
SUBFACTOR_EXTRACTION = OFF;
MULTI_LEVEL_FACTORING = OFF;
RESYNTHESIZE_NETWORK = ON;
USE_LPM_FOR_AHDL_OPERATORS = OFF;
REGISTER_OPTIMIZATION = OFF;
END;
DEFINE_LOGIC_SYNTHESIS_STYLE WYSIWYG.FLEX8000
BEGIN
CASCADE_CHAIN = MANUAL;
CASCADE_CHAIN_LENGTH = 2;
CARRY_CHAIN = MANUAL;
CARRY_CHAIN_LENGTH = 32;
MINIMIZATION = PARTIAL;
SLOW_SLEW_RATE = OFF;
XOR_SYNTHESIS = OFF;
TURBO_BIT = OFF;
PARALLEL_EXPANDERS = OFF;
IGNORE_SOFT_BUFFERS = ON;
SOFT_BUFFER_INSERTION = ON;
DECOMPOSE_GATES = OFF;
REDUCE_LOGIC = OFF;
DUPLICATE_LOGIC_EXTRACTION = OFF;
NOT_GATE_PUSH_BACK = ON;
REFACTORIZATION = OFF;
SUBFACTOR_EXTRACTION = OFF;
MULTI_LEVEL_FACTORING = OFF;
RESYNTHESIZE_NETWORK = OFF;
USE_LPM_FOR_AHDL_OPERATORS = OFF;
REGISTER_OPTIMIZATION = OFF;
END;
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