📄 pems800v055.rpt
字号:
H: LC113 - LC128 16/16(100%) 10/10(100%) 9/16( 56%) 21/36( 58%)
Total dedicated input pins used: 1/4 ( 25%)
Total I/O pins used: 80/80 (100%)
Total logic cells used: 81/128 ( 63%)
Total shareable expanders used: 50/128 ( 39%)
Total Turbo logic cells used: 81/128 ( 63%)
Total shareable expanders not available (n/a): 0/128 ( 0%)
Average fan-in: 6.96
Total fan-in: 564
Total input pins required: 16
Total fast input logic cells required: 0
Total output pins required: 61
Total bidirectional pins required: 0
Total reserved pins required 4
Total logic cells required: 81
Total flipflops required: 0
Total product terms required: 192
Total logic cells lending parallel expanders: 0
Total shareable expanders in database: 50
Synthesized logic cells: 0/ 128 ( 0%)
Device-Specific Information: e:\yp\cpld\dongli\pems800v055.rpt
pems800v055
** INPUTS **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
100 (8) (A) INPUT 0 0 0 0 0 0 4 ALE
3 (3) (A) INPUT 0 0 0 0 0 43 16 A14
4 (1) (A) INPUT 0 0 0 0 0 43 16 A15
89 - - INPUT 0 0 0 0 0 5 3 D0
99 (9) (A) INPUT 0 0 0 0 0 5 3 D1
94 (16) (A) INPUT 0 0 0 0 0 5 3 D2
96 (13) (A) INPUT 0 0 0 0 0 4 3 D3
98 (11) (A) INPUT 0 0 0 0 0 4 2 D4
9 (27) (B) INPUT 0 0 0 0 0 5 2 D5
11 (24) (B) INPUT 0 0 0 0 0 3 2 D6
12 (22) (B) INPUT 0 0 0 0 0 3 2 D7
10 (25) (B) INPUT 0 0 0 0 0 1 0 INT_COMI
95 (14) (A) INPUT 0 0 0 0 0 7 0 RD
1 (6) (A) INPUT 0 0 0 0 0 18 0 RESET
8 (29) (B) INPUT 0 0 0 0 0 1 0 T/R
2 (5) (A) INPUT 0 0 0 0 0 39 16 WR
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: e:\yp\cpld\dongli\pems800v055.rpt
pems800v055
** OUTPUTS **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
85 125 H OUTPUT t 1 0 0 4 5 1 0 AD_A
73 109 G OUTPUT t 1 0 0 4 5 1 0 AD_B
57 86 F OUTPUT t 1 0 0 4 5 1 0 AD_C
44 69 E OUTPUT t 1 0 0 4 5 1 0 BEER
22 41 C OUTPUT t 0 0 0 4 4 0 0 /CS_COM
21 43 C OUTPUT t 0 0 0 3 4 0 0 /CS_KT
19 45 C OUTPUT t 0 0 0 3 4 0 0 /CS_SW
72 107 G OUTPUT t 0 0 0 5 4 0 0 /CS_T
49 75 E OUTPUT t 1 0 0 4 5 1 0 EA0
42 65 E OUTPUT t 1 0 0 4 5 1 0 EA1
30 62 D OUTPUT t 1 0 0 4 5 1 0 EA2
56 85 F OUTPUT t 1 0 0 4 5 1 0 EA3
37 53 D OUTPUT t 1 0 0 4 5 1 0 EA4
82 121 H OUTPUT t 1 0 0 4 5 1 0 EA5
71 105 G OUTPUT t 1 0 0 4 5 1 0 EA6
63 94 F OUTPUT t 1 0 0 4 5 1 0 EA7
46 70 E OUTPUT t 1 0 0 4 5 1 0 EA8
47 72 E OUTPUT t 1 0 0 4 5 1 0 EA9
39 49 D OUTPUT t 1 0 0 4 5 1 0 EA10
54 81 F OUTPUT t 1 0 0 4 5 1 0 EA11
38 51 D OUTPUT t 1 0 0 4 5 1 0 EA12
83 123 H OUTPUT t 1 0 0 4 5 1 0 EA13
65 97 G OUTPUT t 1 0 0 4 5 1 0 EA14
55 83 F OUTPUT t 1 0 0 4 5 1 0 EA15
48 73 E OUTPUT t 1 0 0 4 5 1 0 EA16
50 77 E OUTPUT t 1 0 0 4 5 1 0 EA17
34 56 D OUTPUT t 1 0 0 4 5 1 0 EA18
66 99 G OUTPUT t 0 0 0 5 4 0 0 EM0
29 64 D OUTPUT t 0 0 0 3 4 0 0 E1
78 115 H OUTPUT t 0 0 0 3 4 0 0 E2
26 35 C OUTPUT t 0 0 0 1 0 0 0 INT_COM
25 37 C OUTPUT t 0 0 0 3 4 0 0 I/O_C0
24 38 C OUTPUT t 0 0 0 3 4 0 0 I/O_C1
35 54 D OUTPUT t 1 0 0 4 5 1 0 LED_ARALM
18 46 C OUTPUT t 1 0 0 4 5 1 0 LED_COM1
31 61 D OUTPUT t 1 0 0 4 5 1 0 LED_COM2
79 117 H OUTPUT t 1 0 0 4 5 1 0 LED_COM3
52 80 E OUTPUT t 1 0 0 4 5 1 0 PX11
51 78 E OUTPUT t 1 0 0 4 5 1 0 PX12
33 57 D OUTPUT t 1 0 0 4 5 1 0 PX13
27 33 C OUTPUT t 1 0 0 4 5 1 0 PX21
32 59 D OUTPUT t 1 0 0 4 5 1 0 PX22
80 118 H OUTPUT t 1 0 0 4 5 1 0 PX23
86 126 H OUTPUT t 0 0 0 1 1 0 0 RLC0
15 19 B OUTPUT t 0 0 0 1 1 0 0 RLC1
7 30 B OUTPUT t 0 0 0 1 1 0 0 RLC2
14 21 B OUTPUT t 0 0 0 1 1 0 0 RLC3
16 17 B OUTPUT t 0 0 0 1 1 0 0 RLC4
77 113 H OUTPUT t 0 0 0 1 1 0 0 RLC5
70 104 G OUTPUT t 0 0 0 1 1 0 0 RLC6
60 91 F OUTPUT t 0 0 0 1 1 0 0 RLC7
87 128 H OUTPUT t 0 0 0 1 1 0 0 RLC8
69 102 G OUTPUT t 0 0 0 1 1 0 0 RLC9
67 101 G OUTPUT t 0 0 0 1 1 0 0 RLC10
59 89 F OUTPUT t 0 0 0 1 1 0 0 RLC11
58 88 F OUTPUT t 0 0 0 1 1 0 0 RLC12
81 120 H OUTPUT t 0 0 0 1 1 0 0 RLC13
74 110 G OUTPUT t 0 0 0 1 1 0 0 RLC14
62 93 F OUTPUT t 0 0 0 1 1 0 0 RLC15
43 67 E OUTPUT t 1 0 0 4 5 1 0 SMOG
23 40 C OUTPUT t 0 0 0 1 0 0 0 T/R1
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: e:\yp\cpld\dongli\pems800v055.rpt
pems800v055
** BURIED LOGIC **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
- 116 H LCELL t 0 0 0 2 1 43 17 |74373:3|:12
- 114 H LCELL t 0 0 0 2 1 43 17 |74373:3|:13
- 98 G LCELL t 0 0 0 2 1 43 17 |74373:3|:14
- 95 F LCELL t 0 0 0 2 1 43 17 |74373:3|:15
- 119 H LCELL t 1 0 0 4 5 1 1 |74373:17|:12
- 106 G LCELL t 1 0 0 4 5 1 1 |74373:17|:13
- 100 G LCELL t 1 0 0 4 5 1 1 |74373:17|:14
- 84 F LCELL t 1 0 0 4 5 1 1 |74373:17|:15
- 82 F LCELL t 1 0 0 4 5 1 1 |74373:17|:16
- 124 H LCELL t 1 0 0 4 5 1 1 |74373:17|:17
- 103 G LCELL t 1 0 0 4 5 1 1 |74373:17|:18
- 87 F LCELL t 1 0 0 4 5 1 1 |74373:17|:19
- 127 H LCELL t 1 0 0 4 5 1 1 |74373:18|:12
- 111 G LCELL t 1 0 0 4 5 1 1 |74373:18|:13
(75) 112 G LCELL t 1 0 0 4 5 1 1 |74373:18|:14
- 90 F LCELL t 1 0 0 4 5 1 1 |74373:18|:15
- 92 F LCELL t 1 0 0 4 5 1 1 |74373:18|:16
- 122 H LCELL t 1 0 0 4 5 1 1 |74373:18|:17
- 108 G LCELL t 1 0 0 4 5 1 1 |74373:18|:18
(64) 96 F LCELL t 1 0 0 4 5 1 1 |74373:18|:19
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: e:\yp\cpld\dongli\pems800v055.rpt
pems800v055
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'B':
Logic cells placed in LAB 'B'
+------- LC19 RLC1
| +----- LC30 RLC2
| | +--- LC21 RLC3
| | | +- LC17 RLC4
| | | |
| | | | Other LABs fed by signals
| | | | that feed LAB 'B'
LC | | | | | A B C D E F G H | Logic cells that feed LAB 'B':
Pin
89 -> - - - - | - - - - * - - * | <-- D0
1 -> * * * * | - * - - - * * * | <-- RESET
LC106-> * - - - | - * - - - - * - | <-- |74373:17|:13
LC100-> - * - - | - * - - - - * - | <-- |74373:17|:14
LC84 -> - - * - | - * - - - * - - | <-- |74373:17|:15
LC82 -> - - - * | - * - - - * - - | <-- |74373:17|:16
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: e:\yp\cpld\dongli\pems800v055.rpt
pems800v055
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'C':
Logic cells placed in LAB 'C'
+----------------- LC41 /CS_COM
| +--------------- LC43 /CS_KT
| | +------------- LC45 /CS_SW
| | | +----------- LC35 INT_COM
| | | | +--------- LC37 I/O_C0
| | | | | +------- LC38 I/O_C1
| | | | | | +----- LC46 LED_COM1
| | | | | | | +--- LC33 PX21
| | | | | | | | +- LC40 T/R1
| | | | | | | | |
| | | | | | | | | Other LABs fed by signals
| | | | | | | | | that feed LAB 'C'
LC | | | | | | | | | | A B C D E F G H | Logic cells that feed LAB 'C':
LC46 -> - - - - - - * - - | - - * - - - - - | <-- LED_COM1
LC33 -> - - - - - - - * - | - - * - - - - - | <-- PX21
Pin
3 -> * * * - * * * * - | - - * * * * * * | <-- A14
4 -> * * * - * * * * - | - - * * * * * * | <-- A15
89 -> - - - - - - - - - | - - - - * - - * | <-- D0
96 -> - - - - - - * * - | - - * - - * - - | <-- D3
10 -> - - - * - - - - - | - - * - - - - - | <-- INT_COMI
95 -> * * * - * * - - - | - - * - - - * - | <-- RD
8 -> - - - - - - - - * | - - * - - - - - | <-- T/R
2 -> * - - - - - * * - | - - * * * * * * | <-- WR
LC116-> * * * - * * * * - | - - * * * * * * | <-- |74373:3|:12
LC114-> * * * - * * * * - | - - * * * * * * | <-- |74373:3|:13
LC98 -> * * * - * * * * - | - - * * * * * * | <-- |74373:3|:14
LC95 -> * * * - * * * * - | - - * * * * * * | <-- |74373:3|:15
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: e:\yp\cpld\dongli\pems800v055.rpt
pems800v055
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'D':
Logic cells placed in LAB 'D'
+------------------- LC62 EA2
| +----------------- LC53 EA4
| | +--------------- LC49 EA10
| | | +------------- LC51 EA12
| | | | +----------- LC56 EA18
| | | | | +--------- LC64 E1
| | | | | | +------- LC54 LED_ARALM
| | | | | | | +----- LC61 LED_COM2
| | | | | | | | +--- LC57 PX13
| | | | | | | | | +- LC59 PX22
| | | | | | | | | |
| | | | | | | | | | Other LABs fed by signals
| | | | | | | | | | that feed LAB 'D'
LC | | | | | | | | | | | A B C D E F G H | Logic cells that feed LAB 'D':
LC62 -> * - - - - - - - - - | - - - * - - - - | <-- EA2
LC53 -> - * - - - - - - - - | - - - * - - - - | <-- EA4
LC49 -> - - * - - - - - - - | - - - * - - - - | <-- EA10
LC51 -> - - - * - - - - - - | - - - * - - - - | <-- EA12
LC56 -> - - - - * - - - - - | - - - * - - - - | <-- EA18
LC54 -> - - - - - - * - - - | - - - * - - - - | <-- LED_ARALM
LC61 -> - - - - - - - * - - | - - - * - - - - | <-- LED_COM2
LC57 -> - - - - - - - - * - | - - - * - - - - | <-- PX13
LC59 -> - - - - - - - - - * | - - - * - - - - | <-- PX22
Pin
3 -> * * * * * * * * * * | - - * * * * * * | <-- A14
4 -> * * * * * * * * * * | - - * * * * * * | <-- A15
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