📄 1.rpt
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RLC8 = LCELL( _EQ045 $ GND);
_EQ045 = _LC116 & !RESET;
-- Node name is 'RLC9'
-- Equation name is 'RLC9', location is LC045, type is output.
RLC9 = LCELL( _EQ046 $ GND);
_EQ046 = _LC127 & !RESET;
-- Node name is 'RLC10'
-- Equation name is 'RLC10', location is LC024, type is output.
RLC10 = LCELL( _EQ047 $ GND);
_EQ047 = _LC112 & !RESET;
-- Node name is 'RLC11'
-- Equation name is 'RLC11', location is LC022, type is output.
RLC11 = LCELL( _EQ048 $ GND);
_EQ048 = _LC103 & !RESET;
-- Node name is 'RLC12'
-- Equation name is 'RLC12', location is LC021, type is output.
RLC12 = LCELL( _EQ049 $ GND);
_EQ049 = _LC071 & !RESET;
-- Node name is 'RLC13'
-- Equation name is 'RLC13', location is LC019, type is output.
RLC13 = LCELL( _EQ050 $ GND);
_EQ050 = _LC068 & !RESET;
-- Node name is 'RLC14'
-- Equation name is 'RLC14', location is LC017, type is output.
RLC14 = LCELL( _EQ051 $ GND);
_EQ051 = _LC066 & !RESET;
-- Node name is 'RLC15'
-- Equation name is 'RLC15', location is LC046, type is output.
RLC15 = LCELL( _EQ052 $ GND);
_EQ052 = _LC114 & !RESET;
-- Node name is 'SMOG' = '|74373:86|:12'
-- Equation name is 'SMOG', type is output
SMOG = LCELL( _EQ053 $ GND);
_EQ053 = A14 & !A15 & D0 & !_LC096 & _LC106 & _LC108 & !_LC111 & !WR
# SMOG & _X030;
_X030 = EXP( A14 & !A15 & !D0 & !_LC096 & _LC106 & _LC108 & !_LC111 & !WR);
-- Node name is 'T/R1'
-- Equation name is 'T/R1', location is LC123, type is output.
T/R1 = LCELL(!T/R $ GND);
-- Node name is '|74373:3|:12'
-- Equation name is '_LC096', type is buried
_LC096 = LCELL( _EQ054 $ GND);
_EQ054 = ALE & D0
# D0 & _LC096
# !ALE & _LC096;
-- Node name is '|74373:3|:13'
-- Equation name is '_LC106', type is buried
_LC106 = LCELL( _EQ055 $ GND);
_EQ055 = ALE & D1
# D1 & _LC106
# !ALE & _LC106;
-- Node name is '|74373:3|:14'
-- Equation name is '_LC108', type is buried
_LC108 = LCELL( _EQ056 $ GND);
_EQ056 = ALE & D2
# D2 & _LC108
# !ALE & _LC108;
-- Node name is '|74373:3|:15'
-- Equation name is '_LC111', type is buried
_LC111 = LCELL( _EQ057 $ GND);
_EQ057 = ALE & D3
# D3 & _LC111
# !ALE & _LC111;
-- Node name is '|74373:17|:12'
-- Equation name is '_LC122', type is buried
_LC122 = LCELL( _EQ058 $ GND);
_EQ058 = !A14 & A15 & D0 & !_LC096 & !_LC106 & !_LC108 & !_LC111 & !WR
# _LC122 & _X031;
_X031 = EXP(!A14 & A15 & !D0 & !_LC096 & !_LC106 & !_LC108 & !_LC111 & !WR);
-- Node name is '|74373:17|:13'
-- Equation name is '_LC124', type is buried
_LC124 = LCELL( _EQ059 $ GND);
_EQ059 = !A14 & A15 & D1 & !_LC096 & !_LC106 & !_LC108 & !_LC111 & !WR
# _LC124 & _X032;
_X032 = EXP(!A14 & A15 & !D1 & !_LC096 & !_LC106 & !_LC108 & !_LC111 & !WR);
-- Node name is '|74373:17|:14'
-- Equation name is '_LC098', type is buried
_LC098 = LCELL( _EQ060 $ GND);
_EQ060 = !A14 & A15 & D2 & !_LC096 & !_LC106 & !_LC108 & !_LC111 & !WR
# _LC098 & _X033;
_X033 = EXP(!A14 & A15 & !D2 & !_LC096 & !_LC106 & !_LC108 & !_LC111 & !WR);
-- Node name is '|74373:17|:15'
-- Equation name is '_LC100', type is buried
_LC100 = LCELL( _EQ061 $ GND);
_EQ061 = !A14 & A15 & D3 & !_LC096 & !_LC106 & !_LC108 & !_LC111 & !WR
# _LC100 & _X034;
_X034 = EXP(!A14 & A15 & !D3 & !_LC096 & !_LC106 & !_LC108 & !_LC111 & !WR);
-- Node name is '|74373:17|:16'
-- Equation name is '_LC076', type is buried
_LC076 = LCELL( _EQ062 $ GND);
_EQ062 = !A14 & A15 & D4 & !_LC096 & !_LC106 & !_LC108 & !_LC111 & !WR
# _LC076 & _X035;
_X035 = EXP(!A14 & A15 & !D4 & !_LC096 & !_LC106 & !_LC108 & !_LC111 & !WR);
-- Node name is '|74373:17|:17'
-- Equation name is '_LC052', type is buried
_LC052 = LCELL( _EQ063 $ GND);
_EQ063 = !A14 & A15 & D5 & !_LC096 & !_LC106 & !_LC108 & !_LC111 & !WR
# _LC052 & _X036;
_X036 = EXP(!A14 & A15 & !D5 & !_LC096 & !_LC106 & !_LC108 & !_LC111 & !WR);
-- Node name is '|74373:17|:18'
-- Equation name is '_LC074', type is buried
_LC074 = LCELL( _EQ064 $ GND);
_EQ064 = !A14 & A15 & D6 & !_LC096 & !_LC106 & !_LC108 & !_LC111 & !WR
# _LC074 & _X037;
_X037 = EXP(!A14 & A15 & !D6 & !_LC096 & !_LC106 & !_LC108 & !_LC111 & !WR);
-- Node name is '|74373:17|:19'
-- Equation name is '_LC119', type is buried
_LC119 = LCELL( _EQ065 $ GND);
_EQ065 = !A14 & A15 & D7 & !_LC096 & !_LC106 & !_LC108 & !_LC111 & !WR
# _LC119 & _X038;
_X038 = EXP(!A14 & A15 & !D7 & !_LC096 & !_LC106 & !_LC108 & !_LC111 & !WR);
-- Node name is '|74373:18|:12'
-- Equation name is '_LC116', type is buried
_LC116 = LCELL( _EQ066 $ GND);
_EQ066 = !A14 & A15 & D0 & _LC096 & !_LC106 & !_LC108 & !_LC111 & !WR
# _LC116 & _X039;
_X039 = EXP(!A14 & A15 & !D0 & _LC096 & !_LC106 & !_LC108 & !_LC111 & !WR);
-- Node name is '|74373:18|:13'
-- Equation name is '_LC127', type is buried
_LC127 = LCELL( _EQ067 $ GND);
_EQ067 = !A14 & A15 & D1 & _LC096 & !_LC106 & !_LC108 & !_LC111 & !WR
# _LC127 & _X040;
_X040 = EXP(!A14 & A15 & !D1 & _LC096 & !_LC106 & !_LC108 & !_LC111 & !WR);
-- Node name is '|74373:18|:14'
-- Equation name is '_LC112', type is buried
_LC112 = LCELL( _EQ068 $ GND);
_EQ068 = !A14 & A15 & D2 & _LC096 & !_LC106 & !_LC108 & !_LC111 & !WR
# _LC112 & _X041;
_X041 = EXP(!A14 & A15 & !D2 & _LC096 & !_LC106 & !_LC108 & !_LC111 & !WR);
-- Node name is '|74373:18|:15'
-- Equation name is '_LC103', type is buried
_LC103 = LCELL( _EQ069 $ GND);
_EQ069 = !A14 & A15 & D3 & _LC096 & !_LC106 & !_LC108 & !_LC111 & !WR
# _LC103 & _X042;
_X042 = EXP(!A14 & A15 & !D3 & _LC096 & !_LC106 & !_LC108 & !_LC111 & !WR);
-- Node name is '|74373:18|:16'
-- Equation name is '_LC071', type is buried
_LC071 = LCELL( _EQ070 $ GND);
_EQ070 = !A14 & A15 & D4 & _LC096 & !_LC106 & !_LC108 & !_LC111 & !WR
# _LC071 & _X043;
_X043 = EXP(!A14 & A15 & !D4 & _LC096 & !_LC106 & !_LC108 & !_LC111 & !WR);
-- Node name is '|74373:18|:17'
-- Equation name is '_LC068', type is buried
_LC068 = LCELL( _EQ071 $ GND);
_EQ071 = !A14 & A15 & D5 & _LC096 & !_LC106 & !_LC108 & !_LC111 & !WR
# _LC068 & _X044;
_X044 = EXP(!A14 & A15 & !D5 & _LC096 & !_LC106 & !_LC108 & !_LC111 & !WR);
-- Node name is '|74373:18|:18'
-- Equation name is '_LC066', type is buried
_LC066 = LCELL( _EQ072 $ GND);
_EQ072 = !A14 & A15 & D6 & _LC096 & !_LC106 & !_LC108 & !_LC111 & !WR
# _LC066 & _X045;
_X045 = EXP(!A14 & A15 & !D6 & _LC096 & !_LC106 & !_LC108 & !_LC111 & !WR);
-- Node name is '|74373:18|:19'
-- Equation name is '_LC114', type is buried
_LC114 = LCELL( _EQ073 $ GND);
_EQ073 = !A14 & A15 & D7 & _LC096 & !_LC106 & !_LC108 & !_LC111 & !WR
# _LC114 & _X046;
_X046 = EXP(!A14 & A15 & !D7 & _LC096 & !_LC106 & !_LC108 & !_LC111 & !WR);
-- Node name is '/CS_COM'
-- Equation name is '/CS_COM', location is LC126, type is output.
/CS_COM = LCELL( _EQ074 $ VCC);
_EQ074 = !A14 & A15 & _LC096 & !_LC106 & _LC108 & !_LC111 & !WR
# !A14 & A15 & _LC096 & !_LC106 & _LC108 & !_LC111 & !RD;
-- Node name is '/CS_KT'
-- Equation name is '/CS_KT', location is LC121, type is output.
/CS_KT = LCELL( _EQ075 $ VCC);
_EQ075 = !A14 & A15 & !_LC096 & _LC106 & !_LC108 & !_LC111 & !RD;
-- Node name is '/CS_SW'
-- Equation name is '/CS_SW', location is LC120, type is output.
/CS_SW = LCELL( _EQ076 $ VCC);
_EQ076 = !A14 & A15 & _LC096 & _LC106 & !_LC108 & !_LC111 & !RD;
-- Node name is '/CS_T'
-- Equation name is '/CS_T', location is LC115, type is output.
/CS_T = LCELL( _EQ077 $ VCC);
_EQ077 = !A14 & A15 & _LC096 & _LC106 & _LC108 & !_LC111 & !RESET & !WR
# !A14 & A15 & _LC096 & _LC106 & _LC108 & !_LC111 & !RD & !RESET;
-- Shareable expanders that are duplicated in multiple LABs:
-- (none)
Project Information e:\yp\cpld\dongli\1.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = on
Rules = FLEX Rules
Logic Synthesis:
Synthesis Type Used = Standard
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'MAX7000S' family
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
PARALLEL_EXPANDERS = off
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SOFT_BUFFER_INSERTION = on
SUBFACTOR_EXTRACTION = on
TURBO_BIT = on
XOR_SYNTHESIS = on
IGNORE_SOFT_BUFFERS = off
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
One-Hot State Machine Encoding = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
ADT PALACE Compilation = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
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