1.rpt

单片的得isp实现的全部资料。大家看看阿

        +----------------- LC33 RLC2
        | +--------------- LC35 RLC3
        | | +------------- LC37 RLC4
        | | | +----------- LC38 RLC5
        | | | | +--------- LC40 RLC6
        | | | | | +------- LC41 RLC7
        | | | | | | +----- LC43 RLC8
        | | | | | | | +--- LC45 RLC9
        | | | | | | | | +- LC46 RLC15
        | | | | | | | | | 
        | | | | | | | | |   Other LABs fed by signals
        | | | | | | | | |   that feed LAB 'C'
LC      | | | | | | | | | | A B C D E F G H |     Logic cells that feed LAB 'C':

Pin
92   -> - - - - - - - - - | - * - - - * - * | <-- RD
80   -> * * * * * * * * * | - * * * - * - * | <-- RESET
91   -> - - - - - - - - - | * * - * * * * * | <-- WR
LC98 -> * - - - - - - - - | - - * - - - * - | <-- |74373:17|:14
LC100-> - * - - - - - - - | - - * - - - * - | <-- |74373:17|:15
LC76 -> - - * - - - - - - | - - * - * - - - | <-- |74373:17|:16
LC52 -> - - - * - - - - - | - - * * - - - - | <-- |74373:17|:17
LC74 -> - - - - * - - - - | - - * - * - - - | <-- |74373:17|:18
LC119-> - - - - - * - - - | - - * - - - - * | <-- |74373:17|:19
LC116-> - - - - - - * - - | - - * - - - - * | <-- |74373:18|:12
LC127-> - - - - - - - * - | - - * - - - - * | <-- |74373:18|:13
LC114-> - - - - - - - - * | - - * - - - - * | <-- |74373:18|:19


* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).


Device-Specific Information:                           e:\yp\cpld\dongli\1.rpt
1

** LOGIC CELL INTERCONNECTIONS **

Logic Array Block 'D':

                     Logic cells placed in LAB 'D'
        +----------- LC54 INT_COM
        | +--------- LC57 LED_COM2
        | | +------- LC56 LED_COM3
        | | | +----- LC62 RLC0
        | | | | +--- LC64 RLC1
        | | | | | +- LC52 |74373:17|:17
        | | | | | | 
        | | | | | |   Other LABs fed by signals
        | | | | | |   that feed LAB 'D'
LC      | | | | | | | A B C D E F G H |     Logic cells that feed LAB 'D':
LC52 -> - - - - - * | - - * * - - - - | <-- |74373:17|:17

Pin
50   -> - * * - - * | * * - * * * * * | <-- A14
49   -> - * * - - * | * * - * * * * * | <-- A15
44   -> - - - - - * | * - - * * * * - | <-- D5
87   -> * - - - - - | - - - * - - - - | <-- INT_COMI
92   -> - - - - - - | - * - - - * - * | <-- RD
80   -> - - - * * - | - * * * - * - * | <-- RESET
91   -> - * * - - * | * * - * * * * * | <-- WR
LC96 -> - * * - - * | * * - * * * * * | <-- |74373:3|:12
LC106-> - * * - - * | * * - * * * * * | <-- |74373:3|:13
LC108-> - * * - - * | * * - * * * * * | <-- |74373:3|:14
LC111-> - * * - - * | * * - * * * * * | <-- |74373:3|:15
LC122-> - - - * - - | - - - * - - - * | <-- |74373:17|:12
LC124-> - - - - * - | - - - * - - - * | <-- |74373:17|:13


* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).


Device-Specific Information:                           e:\yp\cpld\dongli\1.rpt
1

** LOGIC CELL INTERCONNECTIONS **

Logic Array Block 'E':

                       Logic cells placed in LAB 'E'
        +------------- LC80 EA8
        | +----------- LC78 EA18
        | | +--------- LC76 |74373:17|:16
        | | | +------- LC74 |74373:17|:18
        | | | | +----- LC71 |74373:18|:16
        | | | | | +--- LC68 |74373:18|:17
        | | | | | | +- LC66 |74373:18|:18
        | | | | | | | 
        | | | | | | |   Other LABs fed by signals
        | | | | | | |   that feed LAB 'E'
LC      | | | | | | | | A B C D E F G H |     Logic cells that feed LAB 'E':
LC80 -> * - - - - - - | - - - - * - - - | <-- EA8
LC78 -> - * - - - - - | - - - - * - - - | <-- EA18
LC76 -> - - * - - - - | - - * - * - - - | <-- |74373:17|:16
LC74 -> - - - * - - - | - - * - * - - - | <-- |74373:17|:18
LC71 -> - - - - * - - | - * - - * - - - | <-- |74373:18|:16
LC68 -> - - - - - * - | - * - - * - - - | <-- |74373:18|:17
LC66 -> - - - - - - * | - * - - * - - - | <-- |74373:18|:18

Pin
50   -> * * * * * * * | * * - * * * * * | <-- A14
49   -> * * * * * * * | * * - * * * * * | <-- A15
37   -> * - - - - - - | * - - - * * * * | <-- D0
39   -> - * - - - - - | * - - - * * * - | <-- D2
43   -> - - * - * - - | * - - - * - * - | <-- D4
44   -> - - - - - * - | * - - * * * * - | <-- D5
46   -> - - - * - - * | * - - - * - * - | <-- D6
92   -> - - - - - - - | - * - - - * - * | <-- RD
91   -> * * * * * * * | * * - * * * * * | <-- WR
LC96 -> * * * * * * * | * * - * * * * * | <-- |74373:3|:12
LC106-> * * * * * * * | * * - * * * * * | <-- |74373:3|:13
LC108-> * * * * * * * | * * - * * * * * | <-- |74373:3|:14
LC111-> * * * * * * * | * * - * * * * * | <-- |74373:3|:15


* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).


Device-Specific Information:                           e:\yp\cpld\dongli\1.rpt
1

** LOGIC CELL INTERCONNECTIONS **

Logic Array Block 'F':

                             Logic cells placed in LAB 'F'
        +------------------- LC89 EA0
        | +----------------- LC91 EA1
        | | +--------------- LC93 EA2
        | | | +------------- LC94 EA3
        | | | | +----------- LC85 EA9
        | | | | | +--------- LC86 EA10
        | | | | | | +------- LC83 EA11
        | | | | | | | +----- LC81 EA13
        | | | | | | | | +--- LC88 EM0
        | | | | | | | | | +- LC96 |74373:3|:12
        | | | | | | | | | | 
        | | | | | | | | | |   Other LABs fed by signals
        | | | | | | | | | |   that feed LAB 'F'
LC      | | | | | | | | | | | A B C D E F G H |     Logic cells that feed LAB 'F':
LC89 -> * - - - - - - - - - | - - - - - * - - | <-- EA0
LC91 -> - * - - - - - - - - | - - - - - * - - | <-- EA1
LC93 -> - - * - - - - - - - | - - - - - * - - | <-- EA2
LC94 -> - - - * - - - - - - | - - - - - * - - | <-- EA3
LC85 -> - - - - * - - - - - | - - - - - * - - | <-- EA9
LC86 -> - - - - - * - - - - | - - - - - * - - | <-- EA10
LC83 -> - - - - - - * - - - | - - - - - * - - | <-- EA11
LC81 -> - - - - - - - * - - | - - - - - * - - | <-- EA13
LC96 -> * * * * * * * * * * | * * - * * * * * | <-- |74373:3|:12

Pin
77   -> - - - - - - - - - * | - - - - - * * - | <-- ALE
50   -> * * * * * * * * * - | * * - * * * * * | <-- A14
49   -> * * * * * * * * * - | * * - * * * * * | <-- A15
37   -> * - - - - - - - - * | * - - - * * * * | <-- D0
38   -> - * - - * - - - - - | * - - - - * * * | <-- D1
39   -> - - * - - * - - - - | * - - - * * * - | <-- D2
42   -> - - - * - - * - - - | * - - - - * * - | <-- D3
44   -> - - - - - - - * - - | * - - * * * * - | <-- D5
92   -> - - - - - - - - * - | - * - - - * - * | <-- RD
80   -> - - - - - - - - * - | - * * * - * - * | <-- RESET
91   -> * * * * * * * * * - | * * - * * * * * | <-- WR
LC106-> * * * * * * * * * - | * * - * * * * * | <-- |74373:3|:13
LC108-> * * * * * * * * * - | * * - * * * * * | <-- |74373:3|:14
LC111-> * * * * * * * * * - | * * - * * * * * | <-- |74373:3|:15


* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).


Device-Specific Information:                           e:\yp\cpld\dongli\1.rpt
1

** LOGIC CELL INTERCONNECTIONS **

Logic Array Block 'G':

                                         Logic cells placed in LAB 'G'
        +------------------------------- LC97 EA4
        | +----------------------------- LC99 EA5
        | | +--------------------------- LC104 EA6
        | | | +------------------------- LC102 EA7
        | | | | +----------------------- LC105 EA12
        | | | | | +--------------------- LC110 EA14
        | | | | | | +------------------- LC101 EA15
        | | | | | | | +----------------- LC107 EA16
        | | | | | | | | +--------------- LC109 EA17
        | | | | | | | | | +------------- LC106 |74373:3|:13
        | | | | | | | | | | +----------- LC108 |74373:3|:14
        | | | | | | | | | | | +--------- LC111 |74373:3|:15
        | | | | | | | | | | | | +------- LC98 |74373:17|:14
        | | | | | | | | | | | | | +----- LC100 |74373:17|:15
        | | | | | | | | | | | | | | +--- LC112 |74373:18|:14
        | | | | | | | | | | | | | | | +- LC103 |74373:18|:15
        | | | | | | | | | | | | | | | | 
        | | | | | | | | | | | | | | | |   Other LABs fed by signals
        | | | | | | | | | | | | | | | |   that feed LAB 'G'
LC      | | | | | | | | | | | | | | | | | A B C D E F G H |     Logic cells that feed LAB 'G':
LC97 -> * - - - - - - - - - - - - - - - | - - - - - - * - | <-- EA4
LC99 -> - * - - - - - - - - - - - - - - | - - - - - - * - | <-- EA5
LC104-> - - * - - - - - - - - - - - - - | - - - - - - * - | <-- EA6
LC102-> - - - * - - - - - - - - - - - - | - - - - - - * - | <-- EA7
LC105-> - - - - * - - - - - - - - - - - | - - - - - - * - | <-- EA12
LC110-> - - - - - * - - - - - - - - - - | - - - - - - * - | <-- EA14
LC101-> - - - - - - * - - - - - - - - - | - - - - - - * - | <-- EA15
LC107-> - - - - - - - * - - - - - - - - | - - - - - - * - | <-- EA16
LC109-> - - - - - - - - * - - - - - - - | - - - - - - * - | <-- EA17
LC106-> * * * * * * * * * * - - * * * * | * * - * * * * * | <-- |74373:3|:13
LC108-> * * * * * * * * * - * - * * * * | * * - * * * * * | <-- |74373:3|:14
LC111-> * * * * * * * * * - - * * * * * | * * - * * * * * | <-- |74373:3|:15
LC98 -> - - - - - - - - - - - - * - - - | - - * - - - * - | <-- |74373:17|:14
LC100-> - - - - - - - - - - - - - * - - | - - * - - - * - | <-- |74373:17|:15
LC112-> - - - - - - - - - - - - - - * - | - * - - - - * - | <-- |74373:18|:14
LC103-> - - - - - - - - - - - - - - - * | - * - - - - * - | <-- |74373:18|:15

Pin
77   -> - - - - - - - - - * * * - - - - | - - - - - * * - | <-- ALE
50   -> * * * * * * * * * - - - * * * * | * * - * * * * * | <-- A14
49   -> * * * * * * * * * - - - * * * * | * * - * * * * * | <-- A15
37   -> - - - - - - - * - - - - - - - - | * - - - * * * * | <-- D0
38   -> - - - - - - - - * * - - - - - - | * - - - - * * * | <-- D1
39   -> - - - - - - - - - - * - * - * - | * - - - * * * - | <-- D2
42   -> - - - - - - - - - - - * - * - * | * - - - - * * - | <-- D3
43   -> * - - - * - - - - - - - - - - - | * - - - * - * - | <-- D4
44   -> - * - - - - - - - - - - - - - - | * - - * * * * - | <-- D5
46   -> - - * - - * - - - - - - - - - - | * - - - * - * - | <-- D6
47   -> - - - * - - * - - - - - - - - - | - - - - - - * * | <-- D7
92   -> - - - - - - - - - - - - - - - - | - * - - - * - * | <-- RD
91   -> * * * * * * * * * - - - * * * * | * * - * * * * * | <-- WR
LC96 -> * * * * * * * * * - - - * * * * | * * - * * * * * | <-- |74373:3|:12


* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).


Device-Specific Information:                           e:\yp\cpld\dongli\1.rpt
1

** LOGIC CELL INTERCONNECTIONS **

Logic Array Block 'H':

                                 Logic cells placed in LAB 'H'
        +----------------------- LC126 /CS_COM
        | +--------------------- LC121 /CS_KT
        | | +------------------- LC120 /CS_SW
        | | | +----------------- LC115 /CS_T
        | | | | +--------------- LC125 SMOG
        | | | | | +------------- LC123 T/R1
        | | | | | | +----------- LC122 |74373:17|:12
        | | | | | | | +--------- LC124 |74373:17|:13
        | | | | | | | | +------- LC119 |74373:17|:19
        | | | | | | | | | +----- LC116 |74373:18|:12
        | | | | | | | | | | +--- LC127 |74373:18|:13
        | | | | | | | | | | | +- LC114 |74373:18|:19
        | | | | | | | | | | | | 
        | | | | | | | | | | | |   Other LABs fed by signals
        | | | | | | | | | | | |   that feed LAB 'H'
LC      | | | | | | | | | | | | | A B C D E F G H |     Logic cells that feed LAB 'H':
LC125-> - - - - * - - - - - - - | - - - - - - - * | <-- SMOG
LC122-> - - - - - - * - - - - - | - - - * - - - * | <-- |74373:17|:12
LC124-> - - - - - - - * - - - - | - - - * - - - * | <-- |74373:17|:13
LC119-> - - - - - - - - * - - - | - - * - - - - * | <-- |74373:17|:19
LC116-> - - - - - - - - - * - - | - - * - - - - * | <-- |74373:18|:12
LC127-> - - - - - - - - - - * - | - - * - - - - * | <-- |74373:18|:13
LC114-> - - - - - - - - - - - * | - - * - - - - * | <-- |74373:18|:19

Pin
50   -> * * * * * - * * * * * * | * * - * * * * * | <-- A14
49   -> * * * * * - * * * * * * | * * - * * * * * | <-- A15
37   -> - - - - * - * - - * - - | * - - - * * * * | <-- D0
38   -> - - - - - - - * - - * - | * - - - - * * * | <-- D1
47   -> - - - - - - - - * - - * | - - - - - - * * | <-- D7
92   -> * * * * - - - - - - - - | - * - - - * - * | <-- RD
80   -> - - - * - - - - - - - - | - * * * - * - * | <-- RESET
79   -> - - - - - * - - - - - - | - - - - - - - * | <-- T/R
91   -> * - - * * - * * * * * * | * * - * * * * * | <-- WR
LC96 -> * * * * * - * * * * * * | * * - * * * * * | <-- |74373:3|:12
LC106-> * * * * * - * * * * * * | * * - * * * * * | <-- |74373:3|:13
LC108-> * * * * * - * * * * * * | * * - * * * * * | <-- |74373:3|:14
LC111-> * * * * * - * * * * * * | * * - * * * * * | <-- |74373:3|:15


* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).


Device-Specific Information:                           e:\yp\cpld\dongli\1.rpt
1

** EQUATIONS **

ALE      : INPUT;
A14      : INPUT;
A15      : INPUT;
D0       : INPUT;
D1       : INPUT;
D2       : INPUT;