📄 1.rpt
字号:
1
** RESOURCE USAGE **
Shareable External
Logic Array Block Logic Cells I/O Pins Expanders Interconnect
A: LC1 - LC16 10/16( 62%) 10/10(100%) 10/16( 62%) 24/36( 66%)
B: LC17 - LC32 9/16( 56%) 10/10(100%) 0/16( 0%) 14/36( 38%)
C: LC33 - LC48 9/16( 56%) 10/10(100%) 0/16( 0%) 10/36( 27%)
D: LC49 - LC64 6/16( 37%) 8/10( 80%) 1/16( 6%) 13/36( 36%)
E: LC65 - LC80 7/16( 43%) 9/10( 90%) 7/16( 43%) 19/36( 52%)
F: LC81 - LC96 10/16( 62%) 10/10(100%) 8/16( 50%) 23/36( 63%)
G: LC97 - LC112 16/16(100%) 10/10(100%) 13/16( 81%) 29/36( 80%)
H: LC113 - LC128 12/16( 75%) 10/10(100%) 7/16( 43%) 20/36( 55%)
Total dedicated input pins used: 2/4 ( 50%)
Total I/O pins used: 77/80 ( 96%)
Total logic cells used: 79/128 ( 61%)
Total shareable expanders used: 46/128 ( 35%)
Total Turbo logic cells used: 79/128 ( 61%)
Total shareable expanders not available (n/a): 0/128 ( 0%)
Average fan-in: 6.86
Total fan-in: 542
Total input pins required: 16
Total fast input logic cells required: 0
Total output pins required: 59
Total bidirectional pins required: 0
Total reserved pins required 4
Total logic cells required: 79
Total flipflops required: 0
Total product terms required: 182
Total logic cells lending parallel expanders: 0
Total shareable expanders in database: 46
Synthesized logic cells: 0/ 128 ( 0%)
Device-Specific Information: e:\yp\cpld\dongli\1.rpt
1
** INPUTS **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
77 (113) (H) INPUT 0 0 0 0 0 0 4 ALE
50 (77) (E) INPUT 0 0 0 0 0 41 16 A14
49 (75) (E) INPUT 0 0 0 0 0 41 16 A15
37 (53) (D) INPUT 0 0 0 0 0 5 3 D0
38 (51) (D) INPUT 0 0 0 0 0 5 3 D1
39 (49) (D) INPUT 0 0 0 0 0 4 3 D2
42 (65) (E) INPUT 0 0 0 0 0 3 3 D3
43 (67) (E) INPUT 0 0 0 0 0 4 2 D4
44 (69) (E) INPUT 0 0 0 0 0 4 2 D5
46 (70) (E) INPUT 0 0 0 0 0 3 2 D6
47 (72) (E) INPUT 0 0 0 0 0 2 2 D7
87 (128) (H) INPUT 0 0 0 0 0 1 0 INT_COMI
92 - - INPUT 0 0 0 0 0 7 0 RD
80 (118) (H) INPUT 0 0 0 0 0 18 0 RESET
79 (117) (H) INPUT 0 0 0 0 0 1 0 T/R
91 - - INPUT 0 0 0 0 0 37 16 WR
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: e:\yp\cpld\dongli\1.rpt
1
** OUTPUTS **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
1 6 A OUTPUT t 1 0 0 4 5 1 0 AD_A
3 3 A OUTPUT t 1 0 0 4 5 1 0 AD_B
2 5 A OUTPUT t 1 0 0 4 5 1 0 AD_C
4 1 A OUTPUT t 1 0 0 4 5 1 0 BEER
86 126 H OUTPUT t 0 0 0 4 4 0 0 /CS_COM
82 121 H OUTPUT t 0 0 0 3 4 0 0 /CS_KT
81 120 H OUTPUT t 0 0 0 3 4 0 0 /CS_SW
78 115 H OUTPUT t 0 0 0 5 4 0 0 /CS_T
59 89 F OUTPUT t 1 0 0 4 5 1 0 EA0
60 91 F OUTPUT t 1 0 0 4 5 1 0 EA1
62 93 F OUTPUT t 1 0 0 4 5 1 0 EA2
63 94 F OUTPUT t 1 0 0 4 5 1 0 EA3
65 97 G OUTPUT t 1 0 0 4 5 1 0 EA4
66 99 G OUTPUT t 1 0 0 4 5 1 0 EA5
70 104 G OUTPUT t 1 0 0 4 5 1 0 EA6
69 102 G OUTPUT t 1 0 0 4 5 1 0 EA7
52 80 E OUTPUT t 1 0 0 4 5 1 0 EA8
56 85 F OUTPUT t 1 0 0 4 5 1 0 EA9
57 86 F OUTPUT t 1 0 0 4 5 1 0 EA10
55 83 F OUTPUT t 1 0 0 4 5 1 0 EA11
71 105 G OUTPUT t 1 0 0 4 5 1 0 EA12
54 81 F OUTPUT t 1 0 0 4 5 1 0 EA13
74 110 G OUTPUT t 1 0 0 4 5 1 0 EA14
67 101 G OUTPUT t 1 0 0 4 5 1 0 EA15
72 107 G OUTPUT t 1 0 0 4 5 1 0 EA16
73 109 G OUTPUT t 1 0 0 4 5 1 0 EA17
51 78 E OUTPUT t 1 0 0 4 5 1 0 EA18
58 88 F OUTPUT t 0 0 0 5 4 0 0 EM0
7 30 B OUTPUT t 0 0 0 3 4 0 0 E1
8 29 B OUTPUT t 0 0 0 3 4 0 0 E2
35 54 D OUTPUT t 0 0 0 1 0 0 0 INT_COM
9 27 B OUTPUT t 0 0 0 3 4 0 0 I/O_C0
10 25 B OUTPUT t 0 0 0 3 4 0 0 I/O_C1
33 57 D OUTPUT t 0 0 0 3 4 0 0 LED_COM2
34 56 D OUTPUT t 0 0 0 3 4 0 0 LED_COM3
100 8 A OUTPUT t ! 1 0 0 4 5 1 0 PX11
99 9 A OUTPUT t ! 1 0 0 4 5 1 0 PX12
98 11 A OUTPUT t ! 1 0 0 4 5 1 0 PX13
96 13 A OUTPUT t ! 1 0 0 4 5 1 0 PX21
95 14 A OUTPUT t ! 1 0 0 4 5 1 0 PX22
94 16 A OUTPUT t ! 1 0 0 4 5 1 0 PX23
30 62 D OUTPUT t 0 0 0 1 1 0 0 RLC0
29 64 D OUTPUT t 0 0 0 1 1 0 0 RLC1
27 33 C OUTPUT t 0 0 0 1 1 0 0 RLC2
26 35 C OUTPUT t 0 0 0 1 1 0 0 RLC3
25 37 C OUTPUT t 0 0 0 1 1 0 0 RLC4
24 38 C OUTPUT t 0 0 0 1 1 0 0 RLC5
23 40 C OUTPUT t 0 0 0 1 1 0 0 RLC6
22 41 C OUTPUT t 0 0 0 1 1 0 0 RLC7
21 43 C OUTPUT t 0 0 0 1 1 0 0 RLC8
19 45 C OUTPUT t 0 0 0 1 1 0 0 RLC9
11 24 B OUTPUT t 0 0 0 1 1 0 0 RLC10
12 22 B OUTPUT t 0 0 0 1 1 0 0 RLC11
14 21 B OUTPUT t 0 0 0 1 1 0 0 RLC12
15 19 B OUTPUT t 0 0 0 1 1 0 0 RLC13
16 17 B OUTPUT t 0 0 0 1 1 0 0 RLC14
18 46 C OUTPUT t 0 0 0 1 1 0 0 RLC15
85 125 H OUTPUT t 1 0 0 4 5 1 0 SMOG
83 123 H OUTPUT t 0 0 0 1 0 0 0 T/R1
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: e:\yp\cpld\dongli\1.rpt
1
** BURIED LOGIC **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
(64) 96 F LCELL t 0 0 0 2 1 41 17 |74373:3|:12
- 106 G LCELL t 0 0 0 2 1 41 17 |74373:3|:13
- 108 G LCELL t 0 0 0 2 1 41 17 |74373:3|:14
- 111 G LCELL t 0 0 0 2 1 41 17 |74373:3|:15
- 122 H LCELL t 1 0 0 4 5 1 1 |74373:17|:12
- 124 H LCELL t 1 0 0 4 5 1 1 |74373:17|:13
- 98 G LCELL t 1 0 0 4 5 1 1 |74373:17|:14
- 100 G LCELL t 1 0 0 4 5 1 1 |74373:17|:15
- 76 E LCELL t 1 0 0 4 5 1 1 |74373:17|:16
- 52 D LCELL t 1 0 0 4 5 1 1 |74373:17|:17
- 74 E LCELL t 1 0 0 4 5 1 1 |74373:17|:18
- 119 H LCELL t 1 0 0 4 5 1 1 |74373:17|:19
- 116 H LCELL t 1 0 0 4 5 1 1 |74373:18|:12
- 127 H LCELL t 1 0 0 4 5 1 1 |74373:18|:13
(75) 112 G LCELL t 1 0 0 4 5 1 1 |74373:18|:14
- 103 G LCELL t 1 0 0 4 5 1 1 |74373:18|:15
- 71 E LCELL t 1 0 0 4 5 1 1 |74373:18|:16
- 68 E LCELL t 1 0 0 4 5 1 1 |74373:18|:17
- 66 E LCELL t 1 0 0 4 5 1 1 |74373:18|:18
- 114 H LCELL t 1 0 0 4 5 1 1 |74373:18|:19
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: e:\yp\cpld\dongli\1.rpt
1
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'A':
Logic cells placed in LAB 'A'
+------------------- LC6 AD_A
| +----------------- LC3 AD_B
| | +--------------- LC5 AD_C
| | | +------------- LC1 BEER
| | | | +----------- LC8 PX11
| | | | | +--------- LC9 PX12
| | | | | | +------- LC11 PX13
| | | | | | | +----- LC13 PX21
| | | | | | | | +--- LC14 PX22
| | | | | | | | | +- LC16 PX23
| | | | | | | | | |
| | | | | | | | | | Other LABs fed by signals
| | | | | | | | | | that feed LAB 'A'
LC | | | | | | | | | | | A B C D E F G H | Logic cells that feed LAB 'A':
LC6 -> * - - - - - - - - - | * - - - - - - - | <-- AD_A
LC3 -> - * - - - - - - - - | * - - - - - - - | <-- AD_B
LC5 -> - - * - - - - - - - | * - - - - - - - | <-- AD_C
LC1 -> - - - * - - - - - - | * - - - - - - - | <-- BEER
LC8 -> - - - - * - - - - - | * - - - - - - - | <-- PX11
LC9 -> - - - - - * - - - - | * - - - - - - - | <-- PX12
LC11 -> - - - - - - * - - - | * - - - - - - - | <-- PX13
LC13 -> - - - - - - - * - - | * - - - - - - - | <-- PX21
LC14 -> - - - - - - - - * - | * - - - - - - - | <-- PX22
LC16 -> - - - - - - - - - * | * - - - - - - - | <-- PX23
Pin
50 -> * * * * * * * * * * | * * - * * * * * | <-- A14
49 -> * * * * * * * * * * | * * - * * * * * | <-- A15
37 -> - - - - * - - - - - | * - - - * * * * | <-- D0
38 -> - - - * - * - - - - | * - - - - * * * | <-- D1
39 -> - - - - - - * - - - | * - - - * * * - | <-- D2
42 -> - - - - - - - * - - | * - - - - * * - | <-- D3
43 -> * - - - - - - - * - | * - - - * - * - | <-- D4
44 -> - * - - - - - - - * | * - - * * * * - | <-- D5
46 -> - - * - - - - - - - | * - - - * - * - | <-- D6
92 -> - - - - - - - - - - | - * - - - * - * | <-- RD
91 -> * * * * * * * * * * | * * - * * * * * | <-- WR
LC96 -> * * * * * * * * * * | * * - * * * * * | <-- |74373:3|:12
LC106-> * * * * * * * * * * | * * - * * * * * | <-- |74373:3|:13
LC108-> * * * * * * * * * * | * * - * * * * * | <-- |74373:3|:14
LC111-> * * * * * * * * * * | * * - * * * * * | <-- |74373:3|:15
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: e:\yp\cpld\dongli\1.rpt
1
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'B':
Logic cells placed in LAB 'B'
+----------------- LC30 E1
| +--------------- LC29 E2
| | +------------- LC27 I/O_C0
| | | +----------- LC25 I/O_C1
| | | | +--------- LC24 RLC10
| | | | | +------- LC22 RLC11
| | | | | | +----- LC21 RLC12
| | | | | | | +--- LC19 RLC13
| | | | | | | | +- LC17 RLC14
| | | | | | | | |
| | | | | | | | | Other LABs fed by signals
| | | | | | | | | that feed LAB 'B'
LC | | | | | | | | | | A B C D E F G H | Logic cells that feed LAB 'B':
Pin
50 -> * * * * - - - - - | * * - * * * * * | <-- A14
49 -> * * * * - - - - - | * * - * * * * * | <-- A15
92 -> - - * * - - - - - | - * - - - * - * | <-- RD
80 -> - - - - * * * * * | - * * * - * - * | <-- RESET
91 -> * * - - - - - - - | * * - * * * * * | <-- WR
LC96 -> * * * * - - - - - | * * - * * * * * | <-- |74373:3|:12
LC106-> * * * * - - - - - | * * - * * * * * | <-- |74373:3|:13
LC108-> * * * * - - - - - | * * - * * * * * | <-- |74373:3|:14
LC111-> * * * * - - - - - | * * - * * * * * | <-- |74373:3|:15
LC112-> - - - - * - - - - | - * - - - - * - | <-- |74373:18|:14
LC103-> - - - - - * - - - | - * - - - - * - | <-- |74373:18|:15
LC71 -> - - - - - - * - - | - * - - * - - - | <-- |74373:18|:16
LC68 -> - - - - - - - * - | - * - - * - - - | <-- |74373:18|:17
LC66 -> - - - - - - - - * | - * - - * - - - | <-- |74373:18|:18
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: e:\yp\cpld\dongli\1.rpt
1
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'C':
Logic cells placed in LAB 'C'
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