divide.s

这是我自己写的关于H.264解码反量化(IQ)部分的ARM汇编程序.请版主给以指教,多谢!

        	  ;__value_in_regs struct{unsigned q,r;}
        	  ;udivide(unsigned d,unsigned n)
        	
        	  AREA           Div,CODE,READONLY
        	  EXPORT         udivide
d             RN			 0
r             RN			 1
t 			  RN			 2
q		      RN             3
        	  
udivide
              MOV            q,#0
              RSBS           t,d,r,LSR #3
              BCC            div_3bits
              RSBS           t,d,r,LSR #8
              BCC            div_8bits
              
              MOV			 d,d,LSL #8
              ORR            q,q,#0xFF000000
              RSBS           t,d,r,LSR #4
              BCC            div_4bits
              RSBS           t,d,r,LSR #8
              BCC            div_8bits
              
              MOV            d,d,LSL #8
              ORR            q,q,#0x00FF0000
              RSBS           t,d,r,LSR #8
              MOVCS          d,d,LSL #8
              ORRCS          q,q,#0x0000FF00
              RSBS           t,d,r,LSR #4
              BCC            div_4bits
              RSBS           t,d,#0
              BCS            div_by_0
              
div_loop      
              MOVCS          d,d,LSR #8

div_8bits   
              RSBS           t,d,r,LSR #7
              SUBCS          r,r,d,LSL #7
              ADC            q,q,q
              
              RSBS           t,d,r,LSR #6
              SUBCS          r,r,d,LSL #6
              ADC            q,q,q                
        	  
        	  RSBS           t,d,r,LSR #5
              SUBCS          r,r,d,LSL #5
              ADC            q,q,q
              
              RSBS           t,d,r,LSR #4
              SUBCS          r,r,d,LSL #4
              ADC            q,q,q
              
div_4bits
              RSBS           t,d,r,LSR #3
              SUBCS          r,r,d,LSL #3
              ADC            q,q,q
              
div_3bits     RSBS           t,d,r,LSR #2
              SUBCS          r,r,d,LSL #2
              ADC            q,q,q
              
              RSBS           t,d,r,LSR #1
              SUBCS          r,r,d,LSL #1
              ADC            q,q,q
              
              RSBS           t,d,r
              SUBCS          r,r,d
              ADCS           q,q,q
              
div_next      
              BCS            div_loop
              MOV            R0,q
              MOV            R1,r
              MOV            PC,LR
              
div_by_0
              MOV            R0,#-1
              MOV            R1,#-1
              MOV            PC,LR
              
              
              END