archdefs.h

MIPS YAMON, a famous monitor inc. source, make file and PDF manuals.

#define C0_Wired		$6
#define R_C0_Wired		6
#define R_C0_SelWired		0
#define C0_TLBWIRED		C0_Wired		/* OBSOLETE - DO NOT USE IN NEW CODE */

#define S_WiredIndex		0			/* TLB wired boundary (R/W) */
#define M_WiredIndex		(0x3f << S_WiredIndex)

#define M_Wired0Fields		0xffffffc0
#define M_WiredRFields		0x00000000


#ifdef MIPS_Release2 
/*
 ************************************************************************
 *                H W R E n a   R E G I S T E R   ( 7 )                 *
 ************************************************************************
 * 	
 *  3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
 *  1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
 * |                            0                          | mask  | HWREna
 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
 */

#define C0_HWREna		$7
#define R_C0_HWREna		7
#define R_C0_SelHWREna		0

#define S_HWREnaMask		0			/* Mask bits (R/W) */
#define M_HWREnaMask		(0xF << S_HWREnaMask)

/*
 * The following defines both the individual mask bits, and the RDHWR
 * register numbers that correspond to the masks.
 */
#define S_HWREnaMask_CPUNum 	0
#define M_HWREnaMask_CPUNum 	(1 << S_HWREnaMask_CPUNum)
#define S_HWREnaMask_CycleCount 2
#define M_HWREnaMask_CycleCount (1 << S_HWREnaMask_CycleCount)
#define S_HWREnaMask_SYNCI_Step 1
#define M_HWREnaMask_SYNCI_Step (1 << S_HWREnaMask_SYNCI_Step)
#define S_HWREnaMask_CC 	2
#define M_HWREnaMask_CC 	(1 << S_HWREnaMask_CC)
#define S_HWREnaMask_CCRes 	3
#define M_HWREnaMask_CCRes 	(1 << S_HWREnaMask_CCRes)

#define HWR_CPUNum		$0			/* CPUNum */
#define R_HWR_CPUNum		S_HWREnaMask_CPUNum
#define HWR_SYNCI_Step		$1			/* Address step for SYNCI */
#define R_HWR_SYNCI_Step	S_HWREnaMask_SYNCI_Step
#define HWR_CycleCount		$2			/* Cycle counter */
#define R_HWR_CycleCount	S_HWREnaMask_CycleCount
#define HWR_CC			$2			/* CycleCounter */
#define R_HWR_CC		S_HWREnaMask_CC
#define HWR_CCRes		$3			/* CCRes */
#define R_HWR_CCRes		S_HWREnaMask_CCRes

#define M_HWREna0Fields		0xfffffff0
#define M_HWREnaRFields		0x00000000

#endif /* ifdef MIPS_Release2 */


/*
 ************************************************************************
 *              B A D V A D D R   R E G I S T E R   ( 8 )               *
 ************************************************************************
 * 	
 *  6 // 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
 *  3 // 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
 * +-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
 * |  //                     Bad Virtual Address                        | BadVAddr
 * +-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
 */

#define C0_BadVAddr		$8
#define R_C0_BadVAddr		8
#define R_C0_SelBadVAddr	0
#define C0_BADVADDR		C0_BadVAddr		/* OBSOLETE - DO NOT USE IN NEW CODE */

#define M_BadVAddrOddPage	K_PageSize		/* Even/Odd VA bit for pair of PAs */

#define M_BadVAddr0Fields	0x00000000
#define M_BadVAddrRFields	0xffffffff
#define M_BadVAddr0Fields64	UINT64_C(0x0000000000000000)
#define M_BadVAddrRFields64	UINT64_C(0xffffffffffffffff)

/*
 ************************************************************************
 *                 C O U N T   R E G I S T E R   ( 9 )                  *
 ************************************************************************
 * 	
 *  3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
 *  1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
 * |                         Count Value                           | Count
 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
 */

#define C0_Count		$9
#define R_C0_Count		9
#define R_C0_SelCount		0
#define C0_COUNT		C0_Count		/* OBSOLETE - DO NOT USE IN NEW CODE */

#define M_Count0Fields		0x00000000
#define M_CountRFields		0x00000000


/*
 ************************************************************************
 *              E N T R Y H I   R E G I S T E R   ( 1 0 )               *
 ************************************************************************
 * 	
 *  6 6 6 6 5 // 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
 *  3 2 1 0 9 // 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
 * +-+-+-+-+-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
 * | R | Fill //                 VPN2                 |    0    |     ASID      | EntryHi
 * +-+-+-+-+-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
 */

#define C0_EntryHi		$10
#define R_C0_EntryHi		10
#define R_C0_SelEntryHi		0
#define C0_TLBHI		C0_EntryHi		/* OBSOLETE - DO NOT USE IN NEW CODE */

#define S_EntryHiR64		62			/* Region (R/W) */
#define M_EntryHiR64		UINT64_C(0xc000000000000000)

#ifndef MIPS_SmartMIPS_ASE

#define S_EntryHiVPN2		13			/* VPN/2 (R/W) */
#define M_EntryHiVPN2		(0x7ffff << S_EntryHiVPN2)
#define M_EntryHiVPN264		UINT64_C(0x000000ffffffe000)

#ifdef MIPS_Release2 
#define S_EntryHiVPN2X		11
#define M_EntryHiVPN2X		(0x3 << S_EntryHiVPN2X)
#endif

#define M_EntryHi0Fields	0x00001f00
#define M_EntryHiRFields	0x00000000
#define M_EntryHi0Fields64	UINT64_C(0x0000000000001f00)

#else /* MIPS_SmartMIPS_ASE */

#define S_EntryHiVPN2		(C0_PageGrainMSOne + 1)
#define M_EntryHiVPN2		(((0x1 << (19 + (12 - C0_PageGrainMSOne)))-1)\
				    << S_EntryHiVPN2)
#define M_EntryHiVPN264		(((UINT64_C(0x1) << \
				    (27 + (12 - C0_PageGrainMSOne)))-1)\
				    << S_EntryHiVPN2)

#define M_EntryHi0Fields	(0x00000700 | \
				    (C0_PageGrainValue & M_PageGrainMask))
#define M_EntryHiRFields	0x00000000

#define M_EntryHi0Fields64	(UINT64_C(0x0000000000001f00) | \
				    (C0_PageGrainValue & M_PageGrainMask))

#endif /* MIPS_SmartMIPS_ASE */

#define M_EntryHiRFields64	UINT64_C(0x3fffff0000000000)
#define S_EntryHiASID		0			/* ASID (R/W) */
#define M_EntryHiASID		(0xff << S_EntryHiASID)
#define S_EntryHiVPN_Shf	S_EntryHiVPN2

/*
 ************************************************************************
 *              C O M P A R E   R E G I S T E R   ( 1 1 )               *
 ************************************************************************
 * 	
 *  3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
 *  1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
 * |                        Compare Value                          | Compare
 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
 */

#define C0_Compare		$11
#define R_C0_Compare		11
#define R_C0_SelCompare		0
#define C0_COMPARE		C0_Compare		/* OBSOLETE - DO NOT USE IN NEW CODE */

#define M_Compare0Fields	0x00000000
#define M_CompareRFields	0x00000000


/*
 ************************************************************************
 *               S T A T U S   R E G I S T E R   ( 1 2 )                *
 ************************************************************************
 * 	
 *  3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
 *  1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
 * |C|C|C|C|R|F|R|M|P|B|T|S|M| | R |I|I|I|I|I|I|I|I|K|S|U|U|R|E|E|I|
 * |U|U|U|U|P|R|E|X|X|E|S|R|M| | s |M|M|M|M|M|M|M|M|X|X|X|M|s|R|X|E| Status
 * |3|2|1|0| | | | | |V| | |I| | v |7|6|5|4|3|2|1|0| | | | |v|L|L| |
 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
 */

#define C0_Status		$12
#define R_C0_Status		12
#define R_C0_SelStatus		0
#define C0_SR			C0_Status		/* OBSOLETE - DO NOT USE IN NEW CODE */

#define S_StatusCU		28			/* Coprocessor enable (R/W) */
#define M_StatusCU		(0xf << S_StatusCU)
#define S_StatusCU3		31 			/* No longer used in Release 2 */
#define M_StatusCU3     	(0x1 << S_StatusCU3)
#define S_StatusCU2		30
#define M_StatusCU2		(0x1 << S_StatusCU2)
#define S_StatusCU1		29
#define M_StatusCU1		(0x1 << S_StatusCU1)
#define S_StatusCU0		28
#define M_StatusCU0		(0x1 << S_StatusCU0)
#define S_StatusRP		27			/* Enable reduced power mode (R/W) */
#define M_StatusRP		(0x1 << S_StatusRP)
#define S_StatusFR		26			/* Enable 64-bit FPRs (R/W) */
#define M_StatusFR		(0x1 << S_StatusFR)
#define S_StatusRE		25			/* Enable reverse endian (R/W) */
#define M_StatusRE		(0x1 << S_StatusRE)
#define S_StatusMX		24			/* Enable access to MDMX resources (MIPS64 only) (R/W) */
#define M_StatusMX		(0x1 << S_StatusMX)
#define S_StatusPX		23			/* Enable access to 64-bit instructions/data (MIPS64 only) (R/W) */
#define M_StatusPX		(0x1 << S_StatusPX)
#define S_StatusBEV		22			/* Enable Boot Exception Vectors (R/W) */
#define M_StatusBEV		(0x1 << S_StatusBEV)
#define S_StatusTS		21			/* Denote TLB shutdown (R/W) */
#define M_StatusTS		(0x1 << S_StatusTS)
#define S_StatusSR		20			/* Denote soft reset (R/W) */
#define M_StatusSR		(0x1 << S_StatusSR)
#define S_StatusNMI		19
#define M_StatusNMI		(0x1 << S_StatusNMI)	/* Denote NMI (R/W) */
#define S_StatusIM		8			/* Interrupt mask (R/W) */
#define M_StatusIM		(0xff << S_StatusIM)
#define S_StatusIM7		15
#define M_StatusIM7		(0x1 << S_StatusIM7)
#define S_StatusIM6		14
#define M_StatusIM6		(0x1 << S_StatusIM6)
#define S_StatusIM5		13
#define M_StatusIM5		(0x1 << S_StatusIM5)
#define S_StatusIM4		12
#define M_StatusIM4		(0x1 << S_StatusIM4)
#define S_StatusIM3		11
#define M_StatusIM3		(0x1 << S_StatusIM3)
#define S_StatusIM2		10
#define M_StatusIM2		(0x1 << S_StatusIM2)
#define S_StatusIM1		9
#define M_StatusIM1		(0x1 << S_StatusIM1)
#define S_StatusIM0		8
#define M_StatusIM0		(0x1 << S_StatusIM0)
#define S_StatusIPL     10
#define M_StatusIPL     (0x3f << S_StatusIPL)
#define S_StatusKX		7			/* Enable access to extended kernel addresses (MIPS64 only) (R/W) */
#define M_StatusKX		(0x1 << S_StatusKX)
#define S_StatusSX		6			/* Enable access to extended supervisor addresses (MIPS64 only) (R/W) */
#define M_StatusSX		(0x1 << S_StatusSX)
#define S_StatusUX		5			/* Enable access to extended user addresses (MIPS64 only) (R/W) */
#define M_StatusUX		(0x1 << S_StatusUX)
#define S_StatusKSU		3			/* Two-bit current mode (R/W) */
#define M_StatusKSU		(0x3 << S_StatusKSU)
#define S_StatusUM		4			/* User mode if supervisor mode not implemented (R/W) */
#define M_StatusUM		(0x1 << S_StatusUM)
#define S_StatusSM		3			/* Supervisor mode (R/W) */
#define M_StatusSM		(0x1 << S_StatusSM)
#define S_StatusERL		2			/* Denotes error level (R/W) */
#define M_StatusERL		(0x1 << S_StatusERL)
#define S_StatusEXL		1			/* Denotes exception level (R/W) */
#define M_StatusEXL		(0x1 << S_StatusEXL)
#define S_StatusIE		0			/* Enables interrupts (R/W) */
#define M_StatusIE		(0x1 << S_StatusIE)

#define M_Status0Fields		0x00040000
#define M_StatusRFields		0x058000e0		/* FR, MX, PX, KX, SX, UX unused in MIPS32 */
#define M_Status0Fields64	0x00040000
#define M_StatusRFields64	0x00000000

/*
 * Values in the KSU field
 */
#define K_StatusKSU_U		2			/* User mode in KSU field */
#define K_StatusKSU_S		1			/* Supervisor mode in KSU field */
#define K_StatusKSU_K		0			/* Kernel mode in KSU field */


#ifdef MIPS_Release2  
/*
 ************************************************************************
 *          I N T C T L   R E G I S T E R   ( 1 2, SELECT 1 )           *
 ************************************************************************
 * 	
 *  3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
 *  1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
 * |  I  |  I  |                               |         |         |
 * |  P  |  P  |         0                     |   VS    |   0     |  IntCtl
 * |  T  |  P  |                               |         |         |
 * |  I  |  C  |                               |         |         |
 * |     |  I  |                               |         |         |
 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
 */

#define C0_IntCtl		$12,1
#define R_C0_IntCtl		12
#define R_C0_SelIntCtl		1

#define S_IntCtlIPTI    29
#define M_IntCtlIPTI    (0x7 << S_IntCtlIPTI)
#define S_IntCtlIPPCI   26
#define M_IntCtlIPPCI   (0x7 << S_IntCtlIPPCI)
#define S_IntCtlVS      5
#define M_IntCtlVS      (0x1f << S_IntCtlVS)

#define M_IntCtl0Fields		0x03fffc1f
#define M_IntCtlRFields		0xfc000000

/*
 * Constants in the VS field
 */

#define K_IntCtlVS0	0x00				/* 0 bytes */
#define K_IntCtlVS32	0x01				/* 32 bytes */
#define K_IntCtlVS64	0x02				/* 64 bytes */
#define K_IntCtlVS128	0x04				/* 128 bytes */
#define K_IntCtlVS256	0x08				/* 256 bytes */
#define K_IntCtlVS512	0x10				/* 512 bytes */


/*
 ************************************************************************
 *          S R S C t l   R E G I S T E R   ( 1 2, SELECT 2 )           *
 ************************************************************************
 *   
 *  3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
 *  1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
 * | 0 | HSS   |   0   | EICSS | 0 | ESS   | 0 |  PSS  | 0 | CSS   | : SRSCtl
 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+                                             *  3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
 *
 */

#define C0_SRSCtl		$12,2
#define R_C0_SRSCtl		12
#define R_C0_SelSRSCtl		2

#define S_SRSCtlHSS		26			/* Highest shadow set (R) */
#define W_SRSCtlHSS		4
#define M_SRSCtlHSS		(0xf << S_SRSCtlHSS)
#define S_SRSCtlEICSS		18			/* Exception shadow set (R/W) */
#define W_SRSCtlEICSS		4
#define M_SRSCtlEICSS		(0xf << S_SRSCtlEICSS)
#define S_SRSCtlESS		12			/* Exception shadow set (R/W) */
#define W_SRSCtlESS		4
#define M_SRSCtlESS		(0xf << S_SRSCtlESS)
#define S_SRSCtlPSS		6			/* Previous shadow set (R/W) */
#define W_SRSCtlPSS		4
#define M_SRSCtlPSS		(0xf << S_SRSCtlPSS)
#define S_SRSCtlCSS		0
#define W_SRSCtlCSS		4
#define M_SRSCtlCSS		(0xf << S_SRSCtlCSS)	/* Current Shadow set (R/W) */

#define M_SRSCtl0Fields		0xc3c30c30
#define M_SRSCtlRFields		0x3c3c000f



/*
 ************************************************************************
 *          S R S Map   R E G I S T E R   ( 1 2, SELECT 3  )            *
 ************************************************************************
 *   
 *  3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
 *  1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
 * | SSV7  |  SSV6 |  SSV5 |  SSV4 |  SSV3 |  SSV2 |  SSV1 |  SSV0 | SRSMap
 * +-+-+-+-+-+-+-+-+-+-+-+-