archdefs.h

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#define M_EntryLo0Fields	0x00000000
#define M_EntryLo0Fields64	UINT64_C(0x0000000000000000)
#ifdef MIPS_SmartMIPS_ASE
#define M_EntryLoRFields	0x00000000
#define M_EntryLoRFields64	UINT64_C(0xffffffff00000000)
#else
#define M_EntryLoRFields	0xc0000000
#define M_EntryLoRFields64	UINT64_C(0xffffffffc0000000)
#endif /* MIPS_SmartMIPS_ASE */

/*
 * Cache attribute values in the C field of EntryLo and the
 * K0 field of Config
 */
#define K_CacheAttrCWTnWA	0			/* Cacheable, write-thru, no write allocate */
#define K_CacheAttrCWTWA	1			/* Cacheable, write-thru, write allocate */
#define K_CacheAttrU		2			/* Uncached */
#define K_CacheAttrC		3			/* Cacheable */
#define K_CacheAttrCN		3			/* Cacheable, non-coherent */
#define K_CacheAttrCCE		4			/* Cacheable, coherent, exclusive */
#define K_CacheAttrCCS		5			/* Cacheable, coherent, shared */
#define K_CacheAttrCCU		6			/* Cacheable, coherent, update */
#define K_CacheAttrUA		7			/* Uncached accelerated */


/*
 ************************************************************************
 *              E N T R Y L O 1   R E G I S T E R   ( 3 )               *
 ************************************************************************
 * 	
 *  6 6 6 6 5 // 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
 *  3 2 1 0 9 // 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
 * +-+-+-+-+-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
 * | Fill (0) //| 0 |                     PFN                       |  C  |D|V|G| EntryLo1
 * +-+-+-+-+-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
 */

#define C0_EntryLo1		$3
#define R_C0_EntryLo1		3
#define R_C0_SelEntryLo1	0
#define C0_TLBLO_1		C0_EntryLo1		/* OBSOLETE - DO NOT USE IN NEW CODE */

/*
 * Field definitions are as given for EntryLo0 above
 */


/*
 ************************************************************************
 *               C O N T E X T   R E G I S T E R   ( 4, SELECT 0 )      *
 ************************************************************************
 * 	
 *  6 // 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
 *  3 // 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
 * +-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
 * |  //       PTEBase    |            BadVPN<31:13>            |   0   | Context
 * +-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
 */

#define C0_Context		$4
#define R_C0_Context		4
#define R_C0_SelContext		0
#define C0_CTXT			C0_Context		/* OBSOLETE - DO NOT USE IN NEW CODE */

#ifndef MIPS_SmartMIPS_ASE
#define S_ContextPTEBase	23			/* PTE base (R/W) */
#define S_ContextBadVPN		4			/* BadVPN2 (R) */

#else

/*
 * Definitions for Context as configured by ContextConfig.
 * Assumes that ContextConfigMSOne and ContextConfigLSOne
 * value are available at evaluation time. Whether these
 * are constants, variables, or returned by a function call 
 * is outside the scope of ArchDefs.h
 */

#define S_ContextPTEBase	(C0_ContextConfigMSOne + 1)

#define S_ContextBadVPN		(C0_ContextConfigLSOne)

#endif /* MIPS_SmartMIPS_ASE */

/*
 * Definitions that can be derived from the above two,
 * regardless of whether or not ContextConfig is implemented.
 */

#define M_Context0Fields	((1 << S_ContextBadVPN) - 1)
#define M_ContextRFields	(((1 << S_ContextPTEBase) - 1) \
				  & ~(M_Context0Fields))
#define M_Context0Fields64	((UINT64_C(1) << S_ContextBadVPN) - 1)
#define M_ContextRFields64	(((UINT64_C(1) << S_ContextPTEBase) - 1) \
				  & ~(M_Context0Fields))
#define M_ContextPTEBase	(((1 << S_ContextBadVPN_LS) - 1) \
                                       << S_ContextPTEBase)
#define M_ContextBadVPN		(((1 << (S_ContextPTEBase - S_ContextBadVPN))\
                                  - 1) << S_ContextBadVPN)
/* Position BadVPN to bit 31. */
#define S_ContextBadVPN_LS	(32 - S_ContextPTEBase)
/* Right-justify shifted BadVPN field, i.e. VA bits not in BadVPN2 */
#define S_ContextBadVPN_RS	(32 - (S_ContextPTEBase - S_ContextBadVPN))

#if defined(MIPS_SmartMIPS_ASE) || defined(MIPS_Release2)
/*
 ************************************************************************
 *       C O N T E X T C O N F I G  R E G I S T E R  ( 4, SELECT 1 )    *
 ************************************************************************
 * 	
 *  6 // 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
 *  3 // 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
 * +-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
 * |  //                     VirtualIndex                               |ContextConfig
 * +-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
 *
 * ContextConfig, if implemented, makes the definitions of the Context
 * register "soft".  The number of bits in the PTEBase and BadVPN fields
 * become variable.  The leading zero field of the ContextConfig register
 * corresponds to the set of bits to be treated as a read/write PTEBase
 * field.  The following field of ones corrsponds to the set of bits to
 * be treated as the virtual page number, into which as many high order
 * bits of the VA are copied as there are bits set in the field.
 */

#define C0_ContextConfig	$4,1
#define R_C0_ContextConfig	4	/* Overload */
#define R_C0_SelContextConfig	1

/*
 * It is possible to write definition for the Context register above
 * in terms of the word value of ContextConfig, but with gcc in particular,
 * it is extrememly ineffecient both at compile and run-time. Contex
 * is therefore defined in terms of two values, C0_ContextConfigMSOne
 * and C0_ContextConfigLSOne, which are the bit numbers of the most
 * significant and least significant one-valued bits of the 
 * ContextConfig register.  The default reset values are defined
 * here, BUT SHOULD BE OVERRIDDEN WITH A FUNCTION CALL OR A REFERENCE
 * TO A RUN-TIME VALUE IN ANY DYNAMIC MODEL OF A SmartMIPS CPU.
 */

#ifndef C0_ContextConfigMSOne
#define C0_ContextConfigMSOne	22
#endif /* C0_ContextConfigMSOne */

#ifndef C0_ContextConfigLSOne	
#define C0_ContextConfigLSOne	4
#endif /* C0_ContextConfigLSOne */


#endif /* MIPS_SmartMIPS_ASE */

/*
 ************************************************************************
 *              P A G E M A S K   R E G I S T E R   ( 5, SELECT 0 )     *
 ************************************************************************
 * 	
 *  3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
 *  1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
 * |  0  |             Mask              |            0            | PageMask
 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
 */

#define C0_PageMask		$5
#define R_C0_PageMask		5			/* Mask (R/W) */
#define R_C0_SelPageMask	0
#define C0_PGMASK		C0_PageMask		/* OBSOLETE - DO NOT USE IN NEW CODE */

#ifndef MIPS_SmartMIPS_ASE

#define S_PageMaskMask		13
#define M_PageMaskMask		(0xffff << S_PageMaskMask)
#define S_PageMaskMaskX		11
#define M_PageMaskMaskX		(0x3 << S_PageMaskMaskX)

#define M_PageMask0Fields	0xe0001fff
#define M_PageMaskRFields	0x00000000

/*
 * Values in the Mask field
 */
#define K_PageMask4K		0x0000			/* K_PageMasknn values are values for use */
#define K_PageMask16K		0x0003			/* with KReqPageAttributes or KReqPageMask macros */
#define K_PageMask64K		0x000f
#define K_PageMask256K		0x003f
#define K_PageMask1M		0x00ff
#define K_PageMask4M		0x03ff
#define K_PageMask16M		0x0fff
#define K_PageMask64M		0x3fff
#define K_PageMask256M		0xffff

#else /* MIPS_SmartMIPS_ASE */

/*
 * In a SmartMIPS MMU, the PageGrain register can be used to
 * enable extending the PageMask Mask field downward by another
 * two bits.  The writable/useable bits of PageMask are thus
 * variable, and depend on the value of the PageGrain register.
 */

#define S_PageMaskMask		(C0_PageGrainMSOne + 1)
#define M_PageMaskMask		(((0x1 << (12 + (12 - C0_PageGrainMSOne))) - 1)\
				    << S_PageMaskMask)

#define M_PageMask0Fields	(0xfe0007ff | \
				(C0_PageGrainValue & M_PageGrainMask))
#define M_PageMaskRFields	0x00000000

/*
 * 1K Pages are only possible if the PageGrain Mask field is zero
 */

#define	K_PageMask1K		((0x1 << (10 - C0_PageGrainMSOne)) - 1)
#define M_PageMask1K		(K_PageMask1K << S_PageMaskMask)

/*
 * 2K Pages are possible if the PageGrain Mask field is zero or one.
 */

#define	K_PageMask2K		((0x1 << (11 - C0_PageGrainMSOne)) - 1)
#define M_PageMask2K		(K_PageMask2K << S_PageMaskMask)

/*
 * 4K and larger pages are expressed differently depending on PageGrain
 */

#define	K_PageMask4K		((0x1 << (12 - C0_PageGrainMSOne)) - 1)
#define	K_PageMask16K		((0x1 << (14 - C0_PageGrainMSOne)) - 1)
#define	K_PageMask64K		((0x1 << (16 - C0_PageGrainMSOne)) - 1)
#define	K_PageMask256K		((0x1 << (18 - C0_PageGrainMSOne)) - 1)
#define	K_PageMask1M		((0x1 << (20 - C0_PageGrainMSOne)) - 1)
#define	K_PageMask4M		((0x1 << (22 - C0_PageGrainMSOne)) - 1)
#define	K_PageMask16M		((0x1 << (24 - C0_PageGrainMSOne)) - 1)
#define	K_PageMask64M		((0x1 << (26 - C0_PageGrainMSOne)) - 1)
#define	K_PageMask256M		((0x1 << (28 - C0_PageGrainMSOne)) - 1)

#endif /* MIPS_SmartMIPS_ASE */

#define M_PageMask4K		(K_PageMask4K << S_PageMaskMask) /* M_PageMasknn values are masks */
#define M_PageMask16K		(K_PageMask16K << S_PageMaskMask) /* in position in the PageMask register */
#define M_PageMask64K		(K_PageMask64K << S_PageMaskMask)
#define M_PageMask256K		(K_PageMask256K << S_PageMaskMask)
#define M_PageMask1M		(K_PageMask1M << S_PageMaskMask)
#define M_PageMask4M		(K_PageMask4M << S_PageMaskMask)
#define M_PageMask16M		(K_PageMask16M << S_PageMaskMask)
#define M_PageMask64M		(K_PageMask64M << S_PageMaskMask)
#define M_PageMask256M		(K_PageMask256M << S_PageMaskMask)

/* Shift amounts for different Page Size */
#define S_PAGE1K	10
#define S_PAGE2K	11
#define S_PAGE4K	12
#define S_PAGE16K	14
#define S_PAGE64K	16
#define S_PAGE256K	18
#define S_PAGE1M	20
#define S_PAGE4M	22
#define S_PAGE16M	24
#define S_PAGE64M	26
#define S_PAGE256M	28

#define S_PageMask1K	(S_PAGE1K   + 1)
#define S_PageMask2K	(S_PAGE2K   + 1)
#define S_PageMask4K	(S_PAGE4K   + 1)
#define S_PageMask16K	(S_PAGE16K  + 1)
#define S_PageMask64K	(S_PAGE64K  + 1)
#define S_PageMask256K	(S_PAGE256K + 1)
#define S_PageMask1M	(S_PAGE1M   + 1)
#define S_PageMask4M	(S_PAGE4M   + 1)
#define S_PageMask16M	(S_PAGE16M  + 1)
#define S_PageMask64M	(S_PAGE64M  + 1)
#define S_PageMask256M	(S_PAGE256M + 1)
/* For Release 2 we need to write correct value to pagemask, default to 4k page*/
#define K_1KPAGEMASK	(0x00000)
#define K_2KPAGEMASK	(0x00800)
#define K_4KPAGEMASK	(0x01800)
#define K_16KPAGEMASK	(0x07800)
#define K_64KPAGEMASK	(0x1f800)
#define K_256KPAGEMASK	(0x7f800)
#define K_1MPAGEMASK	(0x1ff800)
#define K_4MPAGEMASK	(0x7ff800)
#define K_16MPAGEMASK	(0x1fff800)
#define K_64MPAGEMASK	(0x7fff800)
#define K_256MPAGEMASK	(0x1ffff800)


#if defined(MIPS_SmartMIPS_ASE) || defined(MIPS_Release2)

/*
 ************************************************************************
 *              P A G E G R A I N   R E G I S T E R   ( 5, SELECT 1 )   *
 ************************************************************************
 * 	
 *  3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
 *  1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
 * | | |E| |                             |   |     |               |
 * |R|X|L|E|                             |   |     |               |
 * |I|I|P|S|          0                  |Msk|1 1 1|       0       | PageGrain
 * |E|E|A|P|                             |   |     |               |
 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
 *
 * The PageGrain register, if implemented, allows for finer grained
 * pages than would be provided by the default behavior of PageMask
 * and EntryHi.  The Mask bits can be cleared to enable 2K or 4K 
 * page granularity.
 */

#define C0_PageGrain		$5,1
#define R_C0_PageGrain		5			/* Mask (R/W) */
#define R_C0_SelPageGrain	1

#define S_PageGrainOnes		8
#define M_PageGrainOnes		(0x7 << S_PageGrainOnes)

#define S_PageGrainMask		11
#define M_PageGrainMask		(0x3 << S_PageGrainMask)

/*
 * To allow full backward compatibility, the RI/XI bits
 * in EntryLo0/EntryLo1 are write-enabled by the corresponding
 * enable bits of PageGrain.
 */
#define S_PageGrainRIE		31	/* Read Inhibit Enable (R/W) */
#define M_PageGrainRIE		(0x1 << S_PageGrainRIE)
#define S_PageGrainXIE		30	/* Execute Inhibit Enable (R/W) */
#define M_PageGrainXIE		(0x1 << S_PageGrainXIE)

#define S_PageGrainELPA		29	/* Large Physical Page support */
#define M_PageGrainELPA		(0x1 << S_PageGrainELPA)
#define S_PageGrainESP		28	/* 1k page support */
#define M_PageGrainESP		(0x1 << S_PageGrainESP)

#if defined(MIPS_SmartMIPS_ASE) && defined(MIPS_Release2)
#define M_PageGrain0Fields	0x0fffe0ff
#define M_PageGrainRFields	0x00000700
#else
#if defined(MIPS_Release2)
#define M_PageGrain0Fields	0xcfffffff
#define M_PageGrainRFields	0x00000000
#else
#define M_PageGrain0Fields	0x3fffe0ff
#define M_PageGrainRFields	0x00000700
#endif
#endif

/*
 * The Value of the PageGrain register affects the observable
 * behavior of PageMask and EntryHi.  These effects are dynamic,
 * and as such THE FOLLOWING SYMBOLS SHOULD BE OVERRIDDEN WITH
 * FUNCTION CALLS OR REFERENCES TO RUN-TIME VARIABLES IN ANY
 * DYNAMIC MODEL OF A SmartMIPS CPU.  They are defined here as
 * contstants with the reset default value.
 */

#ifndef C0_PageGrainMSOne
#define C0_PageGrainMSOne	12
#endif /* C0_PageGrainMSOne */

#define C0_PageGrainValue	((((0x1 << \
			 	(C0_PageGrainMSOne - S_PageGrainMask + 1)) - 1)\
				    <<  S_PageGrainMask) | M_PageGrainOnes)

#endif /* MIPS_SmartMIPS_ASE */

/*
 ************************************************************************
 *                 W I R E D   R E G I S T E R   ( 6 )                  *
 ************************************************************************
 * 	
 *  3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
 *  1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
 * |                            0                      |   Index   | Wired
 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
 */