archdefs.h

MIPS YAMON, a famous monitor inc. source, make file and PDF manuals.

 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
 * |  Opcode |      Immediate      |
 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
 */

#define S_M16_InstnOpcode	11
#define M_M16_InstnOpcode	(0x1f << S_M16_InstnOpcode)
#define S_M16_InstnOffset	0
#define M_M16_InstnOffset	(0x7ff << S_M16_InstnOffset)

/*
 * MIPS16 RI Type
 *
 *  1 1 1 1 1 1
 *  5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
 * |  Opcode | rx  |  Immediate    |
 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
 */

#define	S_M16_InstnRX		8
#define	M_M16_InstnRX		(0x7 << S_M16_InstnRX)
#define S_M16_InstnOffset7	0
#define M_M16_InstnOffset7	(0xff << S_M16_InstnOffset7)

/*
 * MIPS16 Breakpoint Type
 *
 *  1 1 1 1 1 1
 *  5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
 * |  Opcode |   code    |  func   |
 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
 */

#define S_M16_InstnBPcode	5
#define M_M16_InstnBPcode	(0x3f << S_M16_InstnBPcode)

/*
 * MIPS16 RR Type
 *
 *  1 1 1 1 1 1
 *  5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
 * |  Opcode | rx  | ry  |  func   |
 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
 */
/*
 * MIPS16 RRI Type
 *
 *  1 1 1 1 1 1
 *  5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
 * |  Opcode | rx  | ry  |Immediate|
 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
 */

#define	S_M16_InstnRY		5
#define	M_M16_InstnRY		(0x7  << S_M16_InstnRY)
#define S_M16_InstnFunc		0
#define M_M16_InstnFunc		(0x1f << S_M16_InstnFunc)

/*
 * MIPS16 RRR Type
 *
 *  1 1 1 1 1 1
 *  5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
 * |  Opcode | rx  | ry  | rz  | f |
 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
 */

/*
 * MIPS16 Shift1 Type
 *
 *  3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
 *  1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
 * |  Extend | sa[4:0] |5|    0    |  Opcode | rx  | ry  | sa  | f |
 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
 */

#define S_M16_InstnExtendSA4    22
#define M_M16_InstnExtendSA4    (0x1f << S_M16_InstnExtendSA4)
#define S_M16_InstnExtendSA5    21
#define M_M16_InstnExtendSA5    (0x1 << S_M16_InstnExtendSA5)
#define	S_M16_InstnShiftF	0
#define	M_M16_InstnShiftF	(0x3 << S_M16_InstnShiftF)
#define	S_M16_InstnRZ		2
#define	M_M16_InstnRZ		(0x7 << S_M16_InstnRZ)
#define	S_M16_InstnSA		2
#define	M_M16_InstnSA		(0x7 << S_M16_InstnSA)

/*
 * MIPS16 EXTEND
 *
 *  3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1
 *  1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6
 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
 * |  Extend |  [10:5]   | [15:11] |
 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
 */

#define S_M16_InstnExtendOffset15       16
#define M_M16_InstnExtendOffset15	(0x1f << S_M16_InstnExtendOffset15)
#define S_M16_InstnExtendOffset10	21
#define M_M16_InstnExtendOffset10	(0x3f << S_M16_InstnExtendOffset10)

/*
 * MIPS16 RRI-A Type
 *
 *  3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
 *  1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
 * |  Extend |    [10:4]   |[14:11]|  Opcode | rx  | ry  |f| immed |
 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+

 */

#define	S_M16_InstnF		        4
#define	M_M16_InstnF		        (0x1 << S_M16_InstnF)
#define S_M16_InstnOffset3	        0
#define M_M16_InstnOffset3	        (0xf << S_M16_InstnOffset3)
#define S_M16_InstnExtendOffset14       16
#define M_M16_InstnExtendOffset14       (0xf << S_M16_InstnExtendOffset14)
#define S_M16_InstnExtendOffset10_4     20
#define M_M16_InstnExtendOffset10_4     (0x7f << S_M16_InstnExtendOffset10_4)


/*
 * MIPS16 JALX
 *
 *  3 3 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 1
 *  1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
 * |  Opcode |x| [20:16] | [25:21] |         target[15:0]          |
 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
 */

#define S_M16_InstnX		26
#define M_M16_InstnX		(0x1 << S_M16_InstnX)
#define S_M16_InstnTarget2	21
#define M_M16_InstnTarget2	(0x1f << S_M16_InstnTarget2)
#define S_M16_InstnTarget1	16
#define M_M16_InstnTarget1	(0x1f << S_M16_InstnTarget1)
#define S_M16_InstnTarget0	0
#define M_M16_InstnTarget0	(0xffff << S_M16_InstnTarget0)

/*
 * MIPS16 MOVE32R
 *
 *  1 1 1 1 1 1
 *  5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
 * |   I8    |mv32r| 2:0 |4:3| rz  |
 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
 */

#define S_M16_InstnRZ0		0
#define M_M16_InstnRZ0		(0x7 << S_M16_InstnRZ0)
#define S_M16_InstnR32u		3
#define M_M16_InstnR32u		(0x3 << S_M16_InstnR32u)
#define S_M16_InstnR32l		5
#define M_M16_InstnR32l		(0x7 << S_M16_InstnR32l)

/*
 * MIPS16 save/restore
 *
 *  3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
 *  1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
 * |  Extend |xsreg|f[7:4] | aregs |   I8    |svrs |S|a|0|1|frmsize|
 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
 */

#define S_M16_InstnXsregs       24
#define M_M16_InstnXsregs       (0x7 << S_M16_InstnXsregs)
#define S_M16_InstnFrameSize7   20
#define M_M16_InstnFrameSize7   (0xf << S_M16_InstnFrameSize7)
#define S_M16_InstnAregs        16
#define M_M16_InstnAregs        (0xf << S_M16_InstnAregs)
#define S_M16_InstnS		7
#define M_M16_InstnS		(0x1 << S_M16_InstnS)
#define S_M16_InstnRa		6
#define M_M16_InstnRa		(0x1 << S_M16_InstnRa)
#define S_M16_InstnS0		5
#define M_M16_InstnS0		(0x1 << S_M16_InstnS0)
#define S_M16_InstnS1		4
#define M_M16_InstnS1		(0x1 << S_M16_InstnS1)
#define S_M16_InstnFrameSize    0
#define M_M16_InstnFrameSize    (0xf << S_M16_InstnFrameSize)



/*
 *************************************************************************
 *         V I R T U A L   A D D R E S S   D E F I N I T I O N S         *
 *************************************************************************
 */

#ifdef MIPSADDR64
#define A_K0BASE		UINT64_C(0xffffffff80000000)
#define A_K1BASE		UINT64_C(0xffffffffa0000000)
#define A_K2BASE		UINT64_C(0xffffffffc0000000)
#define A_K3BASE		UINT64_C(0xffffffffe0000000)
#define A_REGION		UINT64_C(0xc000000000000000)
#define A_XKPHYS_ATTR		UINT64_C(0x3800000000000000)
#else
#define A_K0BASE		0x80000000
#define A_K1BASE		0xa0000000
#define A_K2BASE		0xc0000000
#define A_K3BASE		0xe0000000
#endif
#define M_KMAPPED		0x40000000		/* KnSEG address is mapped if bit is one */


#ifdef MIPS_Model64

#define S_VMAP64                62
#define M_VMAP64                UINT64_C(0xc000000000000000)

#define K_VMode11               3
#define K_VMode10               2
#define K_VMode01               1
#define K_VMode00               0

#define S_KSEG3                 29
#define M_KSEG3                 (0x7 << S_KSEG3)
#define K_KSEG3                 7

#define S_SSEG                  29
#define M_SSEG                  (0x7 << S_KSEG3)
#define K_SSEG                  6

#define S_KSSEG                 29
#define M_KSSEG                 (0x7 << S_KSEG3)
#define K_KSSEG                 6

#define S_KSEG1                 29
#define M_KSEG1                 (0x7 << S_KSEG3)
#define K_KSEG1                 5

#define S_KSEG0                 29
#define M_KSEG0                 (0x7 << S_KSEG3)
#define K_KSEG0                 4

#define S_XKSEG                 29
#define M_XKSEG                 (0x7 << S_KSEG3)
#define K_XKSEG                 3

#define S_USEG                  31
#define M_USEG                  (0x1 << S_USEG)
#define K_USEG                  0

#define S_EjtagProbeMem         20
#define M_EjtagProbeMem         (0x1 << S_EjtagProbeMem)
#define K_EjtagProbeMem         0



#else

#define S_KSEG3                 29
#define M_KSEG3                 (0x7 << S_KSEG3)
#define K_KSEG3                 7

#define S_KSSEG                 29
#define M_KSSEG                 (0x7 << S_KSSEG)
#define K_KSSEG                 6

#define S_SSEG                  29
#define M_SSEG                  (0x7 << S_SSEG)
#define K_SSEG                  6

#define S_KSEG1                 29
#define M_KSEG1                 (0x7 << S_KSEG1)
#define K_KSEG1                 5

#define S_KSEG0                 29
#define M_KSEG0                 (0x7 << S_KSEG0)
#define K_KSEG0                 4

#define S_KUSEG                 31
#define M_KUSEG                 (0x1 << S_KUSEG)
#define K_KUSEG                 0

#define S_SUSEG                 31
#define M_SUSEG                 (0x1 << S_SUSEG)
#define K_SUSEG                 0

#define S_USEG                  31
#define M_USEG                  (0x1 << S_USEG)
#define K_USEG                  0

#define K_EjtagLower            0xff200000
#define K_EjtagUpper            0xff3fffff

#define S_EjtagProbeMem         20
#define M_EjtagProbeMem         (0x1 << S_EjtagProbeMem)
#define K_EjtagProbeMem         0

#endif



/*
 *************************************************************************
 *   C A C H E   I N S T R U C T I O N   O P E R A T I O N   C O D E S   *
 *************************************************************************
 */

/*
 * Cache encodings
 */
#define K_CachePriI		0			/* Primary Icache */
#define K_CachePriD		1			/* Primary Dcache */
#define K_CachePriU		1			/* Unified primary */
#define K_CacheTerU		2			/* Unified Tertiary */
#define K_CacheSecU		3			/* Unified secondary */


/*
 * Function encodings
 */
#define S_CacheFunc		2			/* Amount to shift function encoding within 5-bit field */
#define K_CacheIndexInv		0			/* Index invalidate */
#define K_CacheIndexWBInv       0			/* Index writeback invalidate */
#define K_CacheIndexLdTag	1			/* Index load tag */
#define K_CacheIndexStTag	2			/* Index store tag */
#define K_CacheHitInv		4			/* Hit Invalidate */
#define K_CacheFill		5			/* Fill (Icache only) */
#define K_CacheHitWBInv		5			/* Hit writeback invalidate */
#define K_CacheHitWB		6			/* Hit writeback */
#define K_CacheFetchLock	7			/* Fetch and lock */

#define ICIndexInv		((K_CacheIndexInv << S_CacheFunc) | K_CachePriI)
#define DCIndexWBInv		((K_CacheIndexWBInv << S_CacheFunc) | K_CachePriD)
#define DCIndexInv		DCIndexWBInv
#define ICIndexLdTag		((K_CacheIndexLdTag << S_CacheFunc) | K_CachePriI)
#define DCIndexLdTag		((K_CacheIndexLdTag << S_CacheFunc) | K_CachePriD)
#define ICIndexStTag		((K_CacheIndexStTag << S_CacheFunc) | K_CachePriI)
#define DCIndexStTag		((K_CacheIndexStTag << S_CacheFunc) | K_CachePriD)
#define ICHitInv		((K_CacheHitInv << S_CacheFunc) | K_CachePriI)
#define DCHitInv		((K_CacheHitInv << S_CacheFunc) | K_CachePriD)
#define ICFill			((K_CacheFill << S_CacheFunc) | K_CachePriI)
#define DCHitWBInv		((K_CacheHitWBInv << S_CacheFunc) | K_CachePriD)
#define DCHitWB			((K_CacheHitWB << S_CacheFunc) | K_CachePriD)
#define ICFetchLock		((K_CacheFetchLock << S_CacheFunc) | K_CachePriI)
#define DCFetchLock		((K_CacheFetchLock << S_CacheFunc) | K_CachePriD)

#define SCIndexWBInv        	((K_CacheIndexWBInv 	<< S_CacheFunc) | K_CacheSecU)
#define SCIndexInv		SCIndexWBInv
#define SCIndexLdTag        	((K_CacheIndexLdTag 	<< S_CacheFunc) | K_CacheSecU)
#define SCIndexStTag        	((K_CacheIndexStTag 	<< S_CacheFunc) | K_CacheSecU)
#define SCHitInv            	((K_CacheHitInv 	<< S_CacheFunc) | K_CacheSecU)
#define SCHitWBInv          	((K_CacheHitWBInv 	<< S_CacheFunc) | K_CacheSecU)
#define SCHitWB             	((K_CacheHitWB 		<< S_CacheFunc)	| K_CacheSecU)

#define TCIndexWBInv        	((K_CacheIndexWBInv 	<< S_CacheFunc) | K_CacheTerU)
#define TCIndexInv		TCIndexWBInv
#define TCIndexLdTag        	((K_CacheIndexLdTag 	<< S_CacheFunc) | K_CacheTerU)
#define TCIndexStTag        	((K_CacheIndexStTag 	<< S_CacheFunc) | K_CacheTerU)
#define TCHitInv            	((K_CacheHitInv 	<< S_CacheFunc) | K_CacheTerU)
#define TCHitWBInv          	((K_CacheHitWBInv 	<< S_CacheFunc) | K_CacheTerU)
#define TCHitWB             	((K_CacheHitWB 		<< S_CacheFunc)	| K_CacheTerU)

/*
 *************************************************************************
 *          P R E F E T C H   I N S T R U C T I O N   H I N T S          *
 *************************************************************************
 */

#define PrefLoad		0
#define PrefStore		1
#define PrefLoadStreamed	4
#define PrefStoreStreamed	5
#define PrefLoadRetained	6
#define PrefStoreRetained	7