sys_api.h

来自「MIPS YAMON, a famous monitor inc. source」· C头文件 代码 · 共 1,385 行 · 第 1/3 页

    UINT32 *data );


/************************************************************************	
 *
 *                          sys_cpu_k0_config
 *  Description :
 *  -------------
 *
 *  Configure K0 field of CP0 CONFIG register
 *
 *  Return values :
 *  ---------------
 *
 *  None
 *
 ************************************************************************/
void 
sys_cpu_k0_config( 
    UINT32 k0 );		/* K0 field to be written		*/


/************************************************************************	
 *
 *                          sys_cpu_l2_enable
 *  Description :
 *  -------------
 *
 *  Enable/disable L2 cache
 *
 *  Return values :
 *  ---------------
 *
 *  None
 *
 ************************************************************************/
void
sys_cpu_l2_enable(
    bool enable );		/* FALSE -> disable, else enable	*/


/************************************************************************
 *
 *                          sys_cpu_configurability
 *  Description :
 *  -------------
 *
 *  Determine cpu configurability
 *
 *  Return values :
 *  ---------------
 *
 *  Mask with the following bit definitions :
 *
 *  Bit 0 : Set if MMU may be configured (TLD -> Fixed)
 *  Bit 1 : Set if cache may be downsized
 *
 ************************************************************************/
UINT32 
sys_cpu_configurability( void );
#define SYS_CPU_CONFIGURABILITY_MMU	1
#define SYS_CPU_CONFIGURABILITY_CACHE	2


/************************************************************************
 *
 *                          sys_cpu_config
 *  Description :
 *  -------------
 *
 *  Configure CPU cache/mmu settings
 *
 *  Return values :
 *  ---------------
 *
 *  None
 *
 ************************************************************************/
void
sys_cpu_config( 
    bool	       icache,
    bool	       dcache,
    bool	       mmu,
    t_sys_cpu_decoded  *setting );


/************************************************************************
 *
 *                          sys_cpu_mmu_config
 *  Description :
 *  -------------
 *
 *  Configure MMU
 *
 *  Return values :
 *  ---------------
 *
 *  None
 *
 ************************************************************************/
void 
sys_cpu_mmu_config(
    UINT8  c8 );


/************************************************************************	
 *
 *                          sys_cpu_type
 *  Description :
 *  -------------
 *
 *  Determine whether we have :
 *
 *  a) 32 or 64 bit CPU
 *  b) MIPS32/MIPS64 CPU or other type.
 *  c) Support for MIPS16e ASE or not.
 *  d) Support for EJTAG or not.
 *  e) Support for FPU or not.
 *  f) Support for hardware cache coherency or not.
 *
 *  Parameters :
 *  ------------
 *
 *  None

 *  Return values :
 *  ---------------
 *
 *  Following global variables are set :
 *
 *  sys_64bit
 *  sys_mips32_64
 *  sys_mips16e
 *  sys_ejtag
 *  sys_arch_rev
 *  sys_fpu
 *  sys_cpu_cache_coherency
 *
 ************************************************************************/
void
sys_cpu_type( void );


/************************************************************************
 *
 *                          sys_wait_ms
 *  Description :
 *  -------------
 *
 *  Wait for the specified interval
 *
 *  Return values :
 *  ---------------
 *
 *  None
 *
 ************************************************************************/
void
sys_wait_ms(
    UINT32 ms );	/* Interval in milliseconds			*/


/************************************************************************
 *
 *                          sys_reg_addr
 *  Description :
 *  -------------
 *
 *  Calc address from base address, register spacing and register offset.
 *  Also, in case of device with different endianness than CPU, adjust
 *  for endianness.
 *
 *  In case the following is true, the 2 lsb of the address need
 *  to be inverted :
 *
 *     1) Endianness of target and CPU are not the same
 *     3) spacing is 1 byte
 *
 *  Supports spacings of 8 bit and 32 bit (not 16 bit)
 *
 *  Return values :
 *  ---------------
 *
 *  address (void pointer)
 *
 ************************************************************************/
void *
sys_reg_addr(
    bool   target_bigend,	/* TRUE  -> target is big endian.
			           FALSE -> target is little endian.	*/
    UINT8  spacing,		/* spacing of regs in bytes		*/
    void  *base,		/* Base address				*/
    UINT32 offset );		/* Offset scaled down by spacing	*/


/************************************************************************
 *
 *                          sys_enable_int
 *  Description :
 *  -------------
 *
 *  Enable interrupt: set IE in CP0-status.
 *  
 *  Return values :
 *  ---------------
 *
 *  None
 *
 ************************************************************************/
void 
sys_enable_int( void );


/************************************************************************
 *
 *                          sys_enable_int_mask
 *  Description :
 *  -------------
 *
 *  Enable specific CPU interrupt.
 *  
 *  Return values :
 *  ---------------
 *
 *  None
 *
 ************************************************************************/
void 
sys_enable_int_mask( 
    UINT32 cpu_int );		/* CPU interrupt 0..7			*/


/************************************************************************
 *
 *                          sys_disable_int_mask
 *  Description :
 *  -------------
 *
 *  Disable specific CPU interrupt.
 *  
 *  Return values :
 *  ---------------
 *
 *  None
 *
 ************************************************************************/
void 
sys_disable_int_mask( 
    UINT32 cpu_int );		/* CPU interrupt 0..7			*/


/************************************************************************
 *
 *                          sys_disable_int
 *  Description :
 *  -------------
 *
 *  Disable interrupt: clear IE in CP0-status.
 *  
 *  Return values :
 *  ---------------
 *
 *  Old IE bit
 *
 ************************************************************************/
UINT32 
sys_disable_int( void );



/************************************************************************
 *
 *                          sys_store_control_regs
 *  Description :
 *  -------------
 *
 *  Store the current values of CP0 and CP1 control registers.
 *  
 *  Return values :
 *  ---------------
 *
 *  None
 *
 ************************************************************************/
UINT32 
sys_store_control_regs(
    t_gdb_regs *context ); 


/************************************************************************
 *
 *                          sys_decode_compid
 *  Description :
 *  -------------
 *
 *  Map Company ID field of CPO PrId register to string with company name.
 *
 *  Return values :
 *  ---------------
 *
 *  None
 *
 ************************************************************************/
char *
sys_decode_compid( 
    UINT8 compid );	/* Company ID field of CP0 PRId register	*/


/************************************************************************
 *
 *                          sys_decode_procid
 *  Description :
 *  -------------
 *
 *  Map processor ID field to string hodling the name of the CPU
 *  
 *  Return values :
 *  ---------------
 *
 *  String holding name of CPU
 *
 ************************************************************************/
char *
sys_decode_procid( void );


/************************************************************************
 *
 *                          sys_validate_range
 *  Description :
 *  -------------
 *
 *  Validate address range (alignment, TLB if mapped address, RAM range).
 *
 *  Return values :
 *  ---------------
 *
 *  OK :		    No error
 *  SHELL_ERROR_ALIGN :     Alignment error
 *  SHELL_ERROR_OVERFLOW :  Range overflow
 *  SHELL_ERROR_TLB :       Mapped address with no match in TLB
 *  SHELL_ERROR_TLB_WP :    Write access to mapped write protected address
 *  SHELL_ERROR_RAM_RANGE : Address in unused RAM space
 *
 ************************************************************************/
UINT32
sys_validate_range(
    UINT32 addr,	/* Start address				*/
    UINT32 count,	/* Byte count					*/
    UINT8  size,	/* Access size (number of bytes)		*/
    bool   write );	/* Write access					*/



/************************************************************************
 *
 *                          sys_cp0_printreg_all
 *  Description :
 *  -------------
 *
 *  Print CP0 registers.
 *
 ************************************************************************/
UINT32
sys_cp0_printreg_all( 
    t_gdb_regs *context ); // If not NULL, this holds the context to be dumped.
			   // If NULL, print current values of all CP0 regs.

/************************************************************************
 *
 *                          sys_cp0_printreg
 *  Description :
 *  -------------
 *
 *  Print value of CP0 register specified by name.
 *
 ************************************************************************/
UINT32
sys_cp0_printreg( 
    char *reg_name ); // Name of register.


/************************************************************************
 *
 *                          sys_cp0_writereg
 *  Description :
 *  -------------
 *
 *  Write to CP0 register specified by name.
 *
 ************************************************************************/
UINT32
sys_cp0_writereg(
    char   *reg_name, // Name of register.
    UINT64 value );   // Value to be written.

#else  /* #ifndef _ASSEMBLER */

EXTERN( sys_processor )
EXTERN( sys_platform )
EXTERN( sys_corecard )
EXTERN( sys_manid )
EXTERN( sys_manpd )

EXTERN( sys_ramsize )

EXTERN( sys_l2_cache )
EXTERN( sys_l2_cache_enabled )
EXTERN( sys_l2_cache_lines )
EXTERN( sys_l2_cache_linesize )
EXTERN( sys_l2_cache_assoc )
EXTERN( sys_icache_linesize )
EXTERN( sys_icache_lines )
EXTERN( sys_icache_assoc )
EXTERN( sys_dcache_linesize )
EXTERN( sys_dcache_lines )
EXTERN( sys_dcache_assoc )

EXTERN( sys_init_icache )
EXTERN( sys_init_dcache )
		
EXTERN( sys_ftext_init )
EXTERN( sys_etext_ram )
EXTERN( sys_fbss )
EXTERN( sys_freemem )

EXTERN( sys_64bit )
EXTERN( sys_mips32_64 )
EXTERN( sys_mips16e )
EXTERN( sys_smallpage_support )
EXTERN( sys_ejtag )
EXTERN( sys_arch_rev )
EXTERN( sys_fpu )

#endif /* #ifndef _ASSEMBLER */


/* Return codes from sys_tlb_lookup() */

#define SYS_TLB_OK		        0
#define SYS_TLB_NOTFOUND		1
#define SYS_TLB_NOTVALID		2
#define SYS_TLB_WP			3

/* Stack size */
#define SYS_STACK_SIZE			0x5000
#define SYS_APPL_STACK_SIZE		0x5000

/*  RAM vector offsets (ie based at 0x80000000) 
 *  for CacheErr, EJTAG and NMI exceptions.
 */
# define SYS_CACHEERR_RAM_VECTOR_OFS     0x100
# define SYS_EJTAG_RAM_VECTOR_OFS        0x300 /* chosen by YAMON */
# define SYS_NMI_RAM_VECTOR_OFS          0x380 /* chosen by YAMON */

#endif /* #ifndef SYS_API_H */