cpu_s.s

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 *                          sys_cp1_read
 *  Description :
 *  -------------
 *  Read CP1 register
 *
 *  a0 holds register number
 *
 *  Return values :
 *  ---------------
 *  v0 = Value read
 *
 ************************************************************************/
LEAF( sys_cp1_read )

	addiu	sp, -8
	sw	ra, 0(sp)
	
	/* Be sure to make CU1 usable */
	MFC0(   t2, C0_Status)
	sw	t2, 4(sp)
	li	v0, M_StatusCU1
	or	v0, t2
	or	v0, M_StatusIE  /* and disable interrupts */
	xor	v0, M_StatusIE
	MTC0(   v0, C0_Status)

        /*  Calc specific CFC1 opcode :
	 *
	 *  CFC1 rt, fs
	 *
	 *  010001 00010 rt fs 00000000000
	 *
	 *  rt[4:0]  = v0 ($2) 
	 *  fs[4:0]  = Value of a0
         */
        li      t0, 0x44400000 | (0x2 << 16)
	sll 	a0, 11
	or  	t0, a0

	/* Store instruction */
	la  	a0, cfc1_location
	sw 	t0, 0(a0)

	/* Whenever an instruction has been stored to KSEG0, we must
	 * make sure the instruction has been flushed to physical memory
	 * and invalidate the corresponding I-Cache line.
	 */
	jal     sys_dcache_flush_addr		/* modifies t1 only */
	nop
	jal	sys_icache_invalidate_addr
	li	a1, 1				/* Flush pipeline */

cfc1_location :
	nop	/* Placeholder for CFC1 operation */

	/* CFC1 has now been performed, so restore cp0_status and return */
	lw	t2, 4(sp)
	MTC0(   t2, C0_Status)

	lw	ra, 0(sp)
	jr	ra
	addiu	sp, 8

END( sys_cp1_read )	


/************************************************************************
 *
 *                          sys_cp1_write
 *  Description :
 *  -------------
 *  Write CP1 register
 *
 *  a0 holds CP1 register number
 *  a1 holds value to be written
 *
 *  Return values :
 *  ---------------
 *  None
 *
 ************************************************************************/
LEAF( sys_cp1_write )

	addiu	sp, -12
	sw	ra, 0(sp)
	sw	a1, 4(sp)
	
	/* Be sure to make CU1 usable */
	MFC0(   t2, C0_Status)
	sw	t2, 8(sp)	
	li	v0, M_StatusCU1
	or	v0, t2
	or	v0, M_StatusIE  /* and disable interrupts */
	xor	v0, M_StatusIE
	MTC0(   v0, C0_Status)

        /*  Calc specific CTC1 opcode :
	 *
	 *  CTC1 rt, fs 
	 *
	 *  010001 00110 rt fs 00000000000
	 *
	 *  rt[4:0]  = a1 ($5)
	 *  fs[4:0]  = Value of a0
         */
	li      t0, 0x44c00000 | (0x5 << 16)
	sll 	a0, 11
	or  	t0, a0

	/* Store instruction */
	la  	a0, ctc1_location
	sw 	t0, 0(a0)
	
	/* Whenever an instruction has been stored to KSEG0, we must
	 * make sure the instruction has been flushed to physical memory
	 * and invalidate the corresponding I-Cache line.
	 */
	jal     sys_dcache_flush_addr		/* modifies t1 only */
	nop
	jal	sys_icache_invalidate_addr
	li	a1, 1				/* Flush pipeline */

	/* Restore a1 (value to be written) */
	lw	a1, 4(sp)
	
ctc1_location :
	nop	/* Placeholder for CTC1 operation */

	/* CTC1 has now been performed, so restore cp0_status and return */
	lw	t2, 8(sp)
	MTC0(   t2, C0_Status)

	lw	ra, 0(sp)
	jr	ra
	addiu	sp, 12

END( sys_cp1_write )	


/******* Functions for access to CP0 registers ******/

	
/************************************************************************
 *
 *                          sys_cp0_read32
 *  Description :
 *  -------------
 *
 *  Read 32 bit CP0 register
 *
 *  a0 holds register number
 *  a1 holds sel field
 *
 *  Return values :
 *  ---------------
 *
 *  v0 = Value read
 *
 ************************************************************************/
LEAF( sys_cp0_read32 )

	/* Look if a0,a1 happen to be C0_Status, sel0 */
	li	t0, R_C0_Status
	bne	a0, t0, 1f
	nop
	bne	a1, zero, 1f
	nop
	MFC0(   v0, C0_Status)
	jr	ra
	nop
	
1:
	/* Reserve space on stack and store ra, C0_Status */
	addiu	sp, -2*4
	sw	ra, 0(sp)

	/* Disable interrupts */
	MFC0(   t2, C0_Status)
	sw	t2, 4(sp)
	or	t2, M_StatusIE
	xor	t2, M_StatusIE
	MTC0(   t2, C0_Status)

        /*  Calc specific MFC0 opcode :
	 *
	 *  MFC0 rt, rd 
	 *
	 *  010000 00000 rt rd 00000000 sel
	 *
	 *  rt[4:0]  = v0 ($2) 
	 *  rd[4:0]  = Value of a0
	 *  sel[2:0] = Value of a1
         */
	
	li      t0, 0x40000000 | (0x2 << 16)
	or  	t0, a1   /* sel */
	sll 	a0, 11
	or  	t0, a0

	/* Store instruction */
	la  	a0, mfc0_location
	sw 	t0, 0(a0)

	/* Whenever an instruction has been stored to KSEG0, we must
	 * make sure the instruction has been flushed to physical memory
	 * and invalidate the corresponding I-Cache line.
	 */
	jal     sys_dcache_flush_addr
	nop
	jal	sys_icache_invalidate_addr
	li	a1, 1				/* Flush pipeline */	

mfc0_location :
	nop	/* Placeholder for MFC0 operation */

	/* MFC0 has now been performed, so restore cp0_status and return */
	lw	t2, 4(sp)
	MTC0(   t2, C0_Status)

	lw      ra, 0(sp)
	jr	ra
	addiu	sp, 2*4

END( sys_cp0_read32 )	


/************************************************************************
 *
 *                          sys_cp0_read64
 *  Description :
 *  -------------
 *
 *  Read 64 bit CP0 register
 *
 *  a0 holds register number
 *  a1 holds sel field
 *
 *  Return values (Note that C-code is compiled for 32 bit !) :
 *  -----------------------------------------------------------
 *
 *  Little endian :
 *  v0 = 32 lsb of value read
 *  v1 = 32 msb of value read 
 *
 *  Big endian :
 *  v0 = 32 msb of value read
 *  v1 = 32 lsb of value read
 *
 ************************************************************************/
LEAF( sys_cp0_read64 )

	/* Reserve space on stack and store ra, C0_Status */
	addiu	sp, -2*4
	sw	ra, 0(sp)

	/* Disable interrupts */
	MFC0(   t2, C0_Status)
	sw	t2, 4(sp)
	or	t2, M_StatusIE
	xor	t2, M_StatusIE
	MTC0(   t2, C0_Status)

        /*  Calc specific DMFC0 opcode :
	 *
	 *  DMFC0 rt, rd 
	 *
	 *  010000 00001 rt rd 00000000 sel
	 *
	 *  rt[4:0]  = v0 ($2) 
	 *  rd[4:0]  = Value of a0
	 *  sel[2:0] = Value of a1
         */
	
	li      t0, 0x40200000 | (0x2 << 16)
	or  	t0, a1   /* sel */
	sll 	a0, 11
	or  	t0, a0

	/* Store instruction */
	la  	a0, dmfc0_location
	sw 	t0, 0(a0)

	/* Whenever an instruction has been stored to KSEG0, we must
	 * make sure the instruction has been flushed to physical memory
	 * and invalidate the corresponding I-Cache line.
	 */
	jal     sys_dcache_flush_addr
	nop
	jal	sys_icache_invalidate_addr
	li	a1, 1				/* Flush pipeline */		

dmfc0_location :
	nop	/* Placeholder for DMFC0 operation */

SET_MIPS3()
#ifdef EB
        move	v1, v0
	dsrl	v0, v1, 32
#else
	dsrl	v1, v0, 32
#endif	
SET_MIPS0()
	
	/* DMFC0 has now been performed, so restore cp0_status and return */
	lw	t2, 4(sp)
	MTC0(   t2, C0_Status)

	lw      ra, 0(sp)
	jr	ra
	addiu	sp, 2*4

END( sys_cp0_read64 )	
	

/************************************************************************
 *
 *                          sys_cp0_write32
 *  Description :
 *  -------------
 *
 *  Write 32 bit CP0 register
 *
 *  a0 holds register number
 *  a1 holds sel field
 *  a2 holds value to be written
 *
 *  Return values :
 *  ---------------
 *
 *  None
 *
 ************************************************************************/
LEAF( sys_cp0_write32 )

	/* Look if a0,a1 happen to be C0_Status, sel0 */
	li	t0, R_C0_Status
	bne	a0, t0, 1f
	nop
	bne	a1, zero, 1f
	nop
	MTC0(   a2, C0_Status)
	jr	ra
	nop
	
1:
	/* Reserve space on stack and store ra, a2, C0_Status */
	addiu	sp, -3*4
	sw	ra, 0(sp)
	sw	a2, 4(sp)	

	/* Disable interrupts */
	MFC0(   t2, C0_Status)
	sw	t2, 8(sp)
	or	t2, M_StatusIE
	xor	t2, M_StatusIE
	MTC0(   t2, C0_Status)

        /*  Calc specific MTC0 opcode :
	 *
	 *  MTC0 rt, rd 
	 *
	 *  010000 00100 rt rd 00000000 sel
	 *
	 *  rt[4:0]  = a2 ($6)
	 *  rd[4:0]  = Value of a0
	 *  sel[2:0] = Value of a1
         */
	
	li      t0, 0x40800000 | (0x6 << 16)
	or  	t0, a1   /* sel */
	sll 	a0, 11
	or  	t0, a0

	/* Store instruction */
	la  	a0, mtc0_location
	sw 	t0, 0(a0)

	/* Whenever an instruction has been stored to KSEG0, we must
	 * make sure the instruction has been flushed to physical memory
	 * and invalidate the corresponding I-Cache line.
	 */
	jal     sys_dcache_flush_addr
	nop
	jal	sys_icache_invalidate_addr
	li	a1, 1				/* Flush pipeline */

	/* Restore a2 (value to be written) */
	lw	a2, 4(sp)		

mtc0_location :
	nop	/* Placeholder for MTC0 operation */

	/* MTC0 has now been performed, so restore cp0_status and return */
	lw	t2, 8(sp)
	MTC0(   t2, C0_Status)

	lw      ra, 0(sp)
	jr	ra
	addiu	sp, 3*4

END( sys_cp0_write32 )	


/************************************************************************
 *
 *                          sys_cp0_write64
 *  Description :
 *  -------------
 *
 *  Write 64 bit CP0 register
 *
 *  a0 holds register number
 *  a1 holds sel field
 *
 *  Little endian (Note that C-code is compiled for 32 bit !) :
 *
 *  a2 holds 32 lsb of value to be written
 *  a3 holds 32 msb of value to be written
 *
 *  Big endian :
 *
 *  a2 holds 32 msb of value to be written
 *  a3 holds 32 lsb of value to be written
 *
 *  Return values :
 *  ---------------
 *
 *  None
 *
 ************************************************************************/
LEAF( sys_cp0_write64 )

SET_MIPS3()
		
	/* Reserve space on stack and store ra, a2, a3, C0_Status */
	addiu	sp, -4*4
	sw	ra, 0(sp)
	sw	a2, 4(sp)
	sw	a3, 8(sp)

	/* Disable interrupts */
	MFC0(   t2, C0_Status)
	sw	t2, 12(sp)
	or	t2, M_StatusIE
	xor	t2, M_StatusIE
	MTC0(   t2, C0_Status)

        /*  Calc specific DMTC0 opcode :
	 *
	 *  DMTC0 rt, rd 
	 *
	 *  010000 00101 rt rd 00000000 sel
	 *
	 *  rt[4:0]  = a2 ($6)
	 *  rd[4:0]  = Value of a0
	 *  sel[2:0] = Value of a1
         */
	
	li      t0, 0x40a00000 | (0x6 << 16)
	or  	t0, a1   /* sel */
	sll 	a0, 11
	or  	t0, a0

	/* Store instruction */
	la  	a0, dmtc0_location
	sw 	t0, 0(a0)

	/* Whenever an instruction has been stored to KSEG0, we must
	 * make sure the instruction has been flushed to physical memory
	 * and invalidate the corresponding I-Cache line.
	 */
	jal     sys_dcache_flush_addr
	nop
	jal	sys_icache_invalidate_addr
	li	a1, 1				/* Flush pipeline */	

	/* Restore a2, a3 (value to be written) */
	lw	a2, 4(sp)
	lw	a3, 8(sp)

#ifdef EB
	dsll	a3, 32
	dsrl	a3, 32 
	dsll	a2, 32
	or	a2, a3
#else
	dsll	a2, 32
	dsrl	a2, 32
	dsll	a3, 32
	or	a2, a3
#endif

dmtc0_location :
	nop	/* Placeholder for DMTC0 operation */

	/* DMTC0 has now been performed, so restore cp0_status and return */
	lw	t2, 12(sp)
	MTC0(   t2, C0_Status)

	lw      ra, 0(sp)
	jr	ra
	addiu	sp, 4*4

SET_MIPS0()
		
END( sys_cp0_write64 )