cpu_s.s

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/************************************************************************
 *
 *  cpu.S
 *
 *  cpu functions
 *
 * ######################################################################
 *
 * mips_start_of_legal_notice
 * 
 * Copyright (c) 2004 MIPS Technologies, Inc. All rights reserved.
 *
 *
 * Unpublished rights (if any) reserved under the copyright laws of the
 * United States of America and other countries.
 *
 * This code is proprietary to MIPS Technologies, Inc. ("MIPS
 * Technologies"). Any copying, reproducing, modifying or use of this code
 * (in whole or in part) that is not expressly permitted in writing by MIPS
 * Technologies or an authorized third party is strictly prohibited. At a
 * minimum, this code is protected under unfair competition and copyright
 * laws. Violations thereof may result in criminal penalties and fines.
 *
 * MIPS Technologies reserves the right to change this code to improve
 * function, design or otherwise. MIPS Technologies does not assume any
 * liability arising out of the application or use of this code, or of any
 * error or omission in such code. Any warranties, whether express,
 * statutory, implied or otherwise, including but not limited to the implied
 * warranties of merchantability or fitness for a particular purpose, are
 * excluded. Except as expressly provided in any written license agreement
 * from MIPS Technologies or an authorized third party, the furnishing of
 * this code does not give recipient any license to any intellectual
 * property rights, including any patent rights, that cover this code.
 *
 * This code shall not be exported, reexported, transferred, or released,
 * directly or indirectly, in violation of the law of any country or
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 * export, reexport, transfer, or release of this code, the laws of the
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 *
 * This code constitutes one or more of the following: commercial computer
 * software, commercial computer software documentation or other commercial
 * items. If the user of this code, or any related documentation of any
 * kind, including related technical data or manuals, is an agency,
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 * ("Government"), the use, duplication, reproduction, release,
 * modification, disclosure, or transfer of this code, or any related
 * documentation of any kind, is restricted in accordance with Federal
 * Acquisition Regulation 12.212 for civilian agencies and Defense Federal
 * Acquisition Regulation Supplement 227.7202 for military agencies. The use
 * of this code by the Government is further restricted in accordance with
 * the terms of the license agreement(s) and/or applicable contract terms
 * and conditions covering this code from MIPS Technologies or an authorized
 * third party.
 *
 *
 *
 * 
 * mips_end_of_legal_notice
 * 
 *
 ************************************************************************/


/************************************************************************
 *  Include files
 ************************************************************************/

#include <sysdefs.h>
#include <mips.h>
#include <sys_api.h>

/************************************************************************
 *  Definitions
 ************************************************************************/

/************************************************************************
 *  Public variables
 ************************************************************************/

/************************************************************************
 *  Static variables
 ************************************************************************/

/************************************************************************
 *  Implementation : Public functions
 ************************************************************************/


	.set noreorder


/************************************************************************
 *
 *                          sys_tlb_lookup
 *  Description :
 *  -------------
 *
 *  Probe TLB for matching entry
 *
 *  a0 holds the virtual address.
 *  a1 holds pointer to an UINT32, which is set to the mapped address.	 
 *  a2 holds pointer to an UINT32, which is set to the pagesize if a
 *     match is found.
 *	
 *  Return values :
 *  ---------------
 *
 *  SYS_TLB_NOTFOUND : No match
 *  SYS_TLB_NOTVALID : Match with valid bit cleared, i.e. not valid
 *  SYS_TLB_WP	     : Match with dirty bit cleared, i.e. write-protected
 *  SYS_TLB_OK	     : Valid and Dirty entry found
 *
 ************************************************************************/
LEAF(sys_tlb_lookup)

	/* Determine whether small pages (1kB pages) are enabled
	 * (MIPS32/64 Release 2 CPUs only).
	 */
	la	t0, sys_smallpage_support
	lb	t0, 0(t0)
	beq	t0, zero, 1f
	nop
	MFC0_SEL_OPCODE( 8 /* t0 */, R_C0_PageGrain, R_C0_SelPageGrain )
	sll	  t0, 31 - S_PageGrainESP
	bltz      t0, sys_tlb_lookup_small
	nop

1:	
	/**** Setup EntryHi ****/

	/* VPN2 */
	li	t0, MSK(19) << 13
	and	t1, a0, t0

	/* ASID */
	MFC0(   t0, C0_EntryHi )
	li	t2, M_EntryHiASID
	and	t0, t2

	or	t1, t0

	MTC0(   t1, C0_EntryHi )

	/**** Probe ****/
	tlbp
	NOPS
	MFC0(   t0, C0_Index )
	
	bgez    t0, entry_found
	nop
	
	/* Not found */		
	li      v0, SYS_TLB_NOTFOUND
	jr      ra
	nop

entry_found:	

	/* Read entry */
	tlbr    
	NOPS

	/* Determine page size */
	MFC0(   t0, C0_PageMask )
	li	t1, MSK( S_PageMaskMask )
	or	t0, t1
	addiu	t0, 1
	srl	t0, t0, 1

	/* Store result */
	sw	t0, 0(a2)

	/**** Determine mapped address ****/
	
	/*  Even/odd page based on Virtual Address bit N,
	 *  where 2^N = pagesize (currently in t0 register).
	 */

	and	t1, t0, a0
	beq	t1, zero, even_page
	nop

odd_page:
	MFC0(   t1, C0_EntryLo1 )
	b	calc_pfn
	nop

even_page:
	MFC0(   t1, C0_EntryLo0 )		

calc_pfn:
	/* Determine PFN */
	srl	t2, t1, S_EntryLoPFN
	sll     t2, t2, 12

	/*  Least Significant Bits are taken from virtual address.
	 *  t0 = pagesize, t2 = PFN, a0 = virtual address
	 */
	addiu   t0, -1        /* Mask with ones for the lsbits */
	nor	t3, t0, zero  /* Mask with ones for the msbits */
	and	t2, t3	      /* Clear lsbits		       */
	and	t0, a0	      /* Get lsbits from virtual addr  */
	or	t2, t0	      /* Setup lsbits		       */

	/* Store result */
	sw	t2, 0(a1)

	/* Determine setting of Valid bit */
	li	t0, M_EntryLoV
	and	t2, t1, t0
	bne	t2, zero, tlb_valid
	nop

	/* Not valid */
	li      v0, SYS_TLB_NOTVALID
	jr	ra 
	nop

tlb_valid :
	/* Determine setting of Dirty bit */
	li	t0, M_EntryLoD
	and	t2, t1, t0
	bne	t2, zero, tlb_ok
	nop

	/* Write protected */
	li      v0, SYS_TLB_WP
	jr	ra 
	nop

tlb_ok :
	li	v0, SYS_TLB_OK	
	jr	ra
	nop

END(sys_tlb_lookup)

	
/************************************************************************
 *
 *                          sys_tlb_lookup_small
 *  Description :
 *  -------------
 *
 *  Same as sys_tlb_lookup except this is used when small pages (1kB)
 *  are enabled (MIPS32/MIPS64 Release 2 CPU only).
 *
 *  Probe TLB for matching entry
 *
 *  a0 holds the virtual address.
 *  a1 holds pointer to an UINT32, which is set to the mapped address.	 
 *  a2 holds pointer to an UINT32, which is set to the pagesize if a
 *     match is found.
 *	
 *  Return values :
 *  ---------------
 *
 *  SYS_TLB_NOTFOUND : No match
 *  SYS_TLB_NOTVALID : Match with valid bit cleared, i.e. not valid
 *  SYS_TLB_WP	     : Match with dirty bit cleared, i.e. write-protected
 *  SYS_TLB_OK	     : Valid and Dirty entry found
 *
 ************************************************************************/
SLEAF(sys_tlb_lookup_small)

	/**** Setup EntryHi ****/

	/* VPN2 */
	li	t0, MSK(21) << 11
	and	t1, a0, t0

	/* ASID */
	MFC0(   t0, C0_EntryHi )
	li	t2, M_EntryHiASID
	and	t0, t2

	or	t1, t0

	MTC0(   t1, C0_EntryHi )

	/**** Probe ****/
	tlbp
	NOPS
	MFC0(   t0, C0_Index )
	
	bgez    t0, entry_found_small
	nop
	
	/* Not found */		
	li      v0, SYS_TLB_NOTFOUND
	jr      ra
	nop

entry_found_small:	

	/* Read entry */
	tlbr    
	NOPS

	/* Determine page size */
	MFC0(   t0, C0_PageMask )
	li	t1, MSK( S_PageMaskMaskX )
	or	t0, t1
	addiu	t0, 1
	srl	t0, t0, 1

	/* Store result */
	sw	t0, 0(a2)

	/**** Determine mapped address ****/
	
	/*  Even/odd page based on Virtual Address bit N,
	 *  where 2^N = pagesize (currently in t0 register).
	 */

	and	t1, t0, a0
	beq	t1, zero, even_page_small
	nop

odd_page_small:
	MFC0(   t1, C0_EntryLo1 )
	b	calc_pfn_small
	nop

even_page_small:
	MFC0(   t1, C0_EntryLo0 )		

calc_pfn_small:
	/* Determine PFN */
	srl	t2, t1, S_EntryLoPFN
	sll     t2, t2, 10

	/*  Least Significant Bits are taken from virtual address.
	 *  t0 = pagesize, t2 = PFN, a0 = virtual address
	 */
	addiu   t0, -1        /* Mask with ones for the lsbits */
	nor	t3, t0, zero  /* Mask with ones for the msbits */
	and	t2, t3	      /* Clear lsbits		       */
	and	t0, a0	      /* Get lsbits from virtual addr  */
	or	t2, t0	      /* Setup lsbits		       */

	/* Store result */
	sw	t2, 0(a1)

	/* Determine setting of Valid bit */
	li	t0, M_EntryLoV
	and	t2, t1, t0
	bne	t2, zero, tlb_valid_small
	nop

	/* Not valid */
	li      v0, SYS_TLB_NOTVALID
	jr	ra 
	nop

tlb_valid_small :
	/* Determine setting of Dirty bit */
	li	t0, M_EntryLoD
	and	t2, t1, t0
	bne	t2, zero, tlb_ok_small
	nop

	/* Write protected */
	li      v0, SYS_TLB_WP
	jr	ra 
	nop

tlb_ok_small :
	li	v0, SYS_TLB_OK	
	jr	ra
	nop

END(sys_tlb_lookup_small)
		
	
/************************************************************************
 *
 *                          sys_tlb_write
 *  Description :
 *  -------------
 *
 *  Write TLB
 *
 *  a0 = pointer to array of 5 words
 * 
 *  array[0] = index
 *  array[1] = pagemask
 *  array[2] = entryhi
 *  array[3] = entrylo0
 *  array[4] = entrylo1
 *	
 *  Return values :
 *  ---------------
 *
 *  None
 *
 ************************************************************************/
LEAF(sys_tlb_write)

	lw    t0, 0(a0)
	MTC0( t0, C0_Index )

	lw    t0, 4(a0)
	MTC0( t0, C0_PageMask )

	lw    t0, 8(a0)
	MTC0( t0, C0_EntryHi )

	lw    t0, 12(a0)
	MTC0( t0, C0_EntryLo0 )

	lw    t0, 16(a0)
	MTC0( t0, C0_EntryLo1 )

	tlbwi

	/* Done */
	jr	ra
	nop

END(sys_tlb_write)


/************************************************************************
 *
 *                          sys_tlb_read
 *  Description :
 *  -------------
 *
 *  Read TLB
 *
 *  a0 = index
 *  a1 = pointer to array of 5 words. They will be filled with the
 *       following data :
 *
 *  array[0] = pagemask
 *  array[1] = entryhi
 *  array[2] = entrylo0
 *  array[3] = entrylo1
 *	
 *  Return values :
 *  ---------------
 *
 *  None
 *
 ************************************************************************/
LEAF(sys_tlb_read)

	MTC0( a0, C0_Index )

	tlbr

	MFC0( t0, C0_PageMask )
	sw    t0, 0(a1)

	MFC0( t0, C0_EntryHi )
	sw    t0, 4(a1)

	MFC0( t0, C0_EntryLo0 )
	sw    t0, 8(a1)

	MFC0( t0, C0_EntryLo1 )
	sw    t0, 12(a1)

	/* Done */
	jr	ra
	nop

END(sys_tlb_read)
	
			
/************************************************************************
 *
 *                          sys_icache_invalidate_index
 *  Description :
 *  -------------
 *
 *  Invalidate I cache line containing specified index
 *
 *  a0 holds the index
 *	
 *  Return values :
 *  ---------------
 *
 *  None
 *
 ************************************************************************/
LEAF(sys_icache_invalidate_index)

SET_MIPS3()
	ICACHE_INDEX_INVALIDATE_OP(a0,a1)
SET_MIPS0()

	jr	ra
	nop
	
END(sys_icache_invalidate_index)


/************************************************************************
 *
 *                          sys_icache_invalidate_addr
 *  Note
 *  ------
 *  This function is called from user2yamon() in application context,
 *  possibly in 64 bit mode and with invalid gp.