📄 gt64120_core.s
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beq t0, zero, error_sdram li v0, ERROR_SDRAM_CASLAT ori ACCUM, (GT_SDRAM_B0_CASLAT_2 << GT_SDRAM_B0_CASLAT_SHF)#define DEV_BANKS s6#define ROWS s7#define COLS s8 /* s0..s8 used */ /* Number of Rows bits */ li a0, SPD_ROWS jal sys_spd_read nop bne v0, zero, error_sdram nop move ROWS, v1 and ROWS, SPD_ROWS_A_MSK srl ROWS, SPD_ROWS_A_SHF /* Number of Column bits */ li a0, SPD_COL jal sys_spd_read nop bne v0, zero, error_sdram nop move COLS, v1 and COLS, COLS, SPD_COL_A_MSK srl COLS, SPD_COL_A_SHF /* SDRAM device banks. * Note : This is the internal bank count of the SDRAM devices, not to * be confused with the module banks of the SDRAM module. */ li a0, SPD_DEVICE_BANKS jal sys_spd_read nop bne v0, zero, error_sdram nop move DEV_BANKS, v1 /* SDRAM device width */ li a0, SPD_SDRAM_WIDTH jal sys_spd_read nop bne v0, zero, error_sdram nop and v1, SPD_SDRAM_WIDTH_W_MSK srl v1, SPD_SDRAM_WIDTH_W_SHF /* Calc SDRAM device size = * dev_width * dev_banks * 2 ^ (rows + columns) */ addu t0, ROWS, COLS#undef ROWS#undef COLS /* s0..s6 used */#define DEV_SIZE s7 /* s0..s7 used */ sll DEV_SIZE, DEV_BANKS, t0 multu DEV_SIZE, v1 mflo DEV_SIZE /* Setup SDRAM device size (16MBit or 64/128Mbit) */ li t0, 16 * 1024 * 1024 /* 16 Mbit */ beq DEV_SIZE, t0, Mbit16 nop ori ACCUM, (GT_SDRAM_B0_SIZE_64M << GT_SDRAM_B0_SIZE_SHF) b burstlen nopMbit16: ori ACCUM, (GT_SDRAM_B0_SIZE_16M << GT_SDRAM_B0_SIZE_SHF)burstlen: /* Burst length field : Galileo only supports burstlen = 8 */ li a0, SPD_BURSTLEN jal sys_spd_read /* v1 = burstlen byte */ nop bne v0, zero, error_sdram nop and t0, v1, SPD_BURSTLEN_8_MSK beq t0, zero, error_sdram li v0, ERROR_SDRAM_BURSTLEN ori ACCUM, (GT_SDRAM_B0_BLEN_8 << GT_SDRAM_B0_BLEN_SHF) /* Parity field : * If SDRAM module supports parity, enable parity support. * else if SDRAM module supports ECC, indicate error. * If SDRAM module does not support any of those, disable * parity support. */ /* Determine Parity support */#define PARITY_SUPPORT s8 /* s0..s8 used */ li a0, SPD_CONFIG_TYPE jal sys_spd_read /* v1 = config type byte */ nop bne v0, zero, error_sdram nop li t0, SPD_CONFIG_TYPE_PARITY beq t0, v1, parity_support nop li t0, SPD_CONFIG_TYPE_ECC beq t0, v1, error_sdram li v0, ERROR_SDRAM_ERRORCHECK b write_banks move PARITY_SUPPORT, zeroparity_support: ori ACCUM, GT_SDRAM_B0_PAR_BIT li PARITY_SUPPORT, 1write_banks: /* Number of device banks */ li t0, 2 beq DEV_BANKS, t0, dev_banks2 li t0, 4 bne DEV_BANKS, t0, error_sdram li v0, ERROR_SDRAM_DEV_BANKSdev_banks4: ori ACCUM, GT_SDRAM_B0_64BITINT_4 << GT_SDRAM_B0_64BITINT_SHF b write_bank_parms nopdev_banks2: ori ACCUM, GT_SDRAM_B0_64BITINT_2 << GT_SDRAM_B0_64BITINT_SHFwrite_bank_parms: move t0, ACCUM GT_SW( ACCUM, GT_SDRAM_B0_OFS, GTBASE ) GT_SW( t0, GT_SDRAM_B2_OFS, GTBASE ) /* SDRAM configuration register */ li ACCUM, GT_SDRAM_CFG_NINTERLEAVE_BIT | GT_SDRAM_CFG_DUPBA_BIT /* Set RefIntCnt based on SDRAM module requirements and * the slowest possible bus frequency. * This may later be changed when the bus freq. is known. */ /* Determine min refresh rate and type */ li a0, SPD_RFSH_RT jal sys_spd_read nop bne v0, zero, error_sdram nop and v1, SPD_RFSH_RT_RATE_MSK srl v1, SPD_RFSH_RT_RATE_SHF li t0, SPD_RFSH_RT_RATE_125 /* 125 us */ beq t0, v1, calc_rfsh_count li t0, 125 li t0, SPD_RFSH_RT_RATE_62_5 /* 62.5 us */ beq t0, v1, calc_rfsh_count li t0, 62 li t0, SPD_RFSH_RT_RATE_31_3 /* 31.3 us */ beq t0, v1, calc_rfsh_count li t0, 31 li t0, SPD_RFSH_RT_RATE_15_625 /* 15.625 us */ beq t0, v1, calc_rfsh_count li t0, 15 li t0, SPD_RFSH_RT_RATE_7_8 /* 7.8 us */ beq t0, v1, calc_rfsh_count li t0, 7 /* assume 3.9us */ li t0, 3calc_rfsh_count: /* RefIntCnt = rate (in us) * lowest frequency (in MHz) */ multu FREQ, t0 mflo t0 /* Make sure the result fits in the REFINT field */ li t1, (GT_SDRAM_CFG_REFINT_MSK >> GT_SDRAM_CFG_REFINT_SHF) sltu t2, t1, t0 beq t2, zero, set_refint nop move t0, t1 /* Set refintcnt = max value */set_refint: /* Add the result to ACCUM */ sll t0, GT_SDRAM_CFG_REFINT_SHF or ACCUM, t0 /* Setup RMW bit : * If parity is enabled AND SDRAM module contains SDRAM * device(s) dedicated to parity (as opposed to SDRAM * modules where parity bit is included in each SDRAM device) * then Enable else Disable. */ beq PARITY_SUPPORT, zero, store_sdram_cfg /* Read Error Checking RAM width */ li a0, SPD_EC_SDRAM jal sys_spd_read nop bne v0, zero, error_sdram nop and v1, SPD_EC_SDRAM_WIDTH_MSK beq v1, zero, store_sdram_cfg noprmw: ori ACCUM, GT_SDRAM_CFG_RMW_BIT store_sdram_cfg : /* Ready to store CALC in SDRAM configuration register */ GT_SW( ACCUM, GT_SDRAM_CFG_OFS, GTBASE ) /**** Setup decoding ****/ /* SCS[1:0] */ move LO, zero add HI, LO, BSIZE0 add REGLO, GTBASE, GT_SCS10LD_OFS add REGHI, GTBASE, GT_SCS10HD_OFS jal setup_cpu_decode nop bne v0, zero, error_sdram nop /* SCS0 */ add REGLO, GTBASE, GT_SCS0LD_OFS add REGHI, GTBASE, GT_SCS0HD_OFS jal setup_dev_decode nop /* SCS1 (not used) */ move HI, zero add REGLO, GTBASE, GT_SCS1LD_OFS add REGHI, GTBASE, GT_SCS1HD_OFS jal setup_dev_decode nop /* SCS[3:2] */ move LO, BSIZE0 add HI, LO, BSIZE1 add REGLO, GTBASE, GT_SCS32LD_OFS add REGHI, GTBASE, GT_SCS32HD_OFS jal setup_cpu_decode nop bne v0, zero, error_sdram nop /* SCS2 */ add REGLO, GTBASE, GT_SCS2LD_OFS add REGHI, GTBASE, GT_SCS2HD_OFS jal setup_dev_decode nop /* SCS3 (not used) */ move HI, zero add REGLO, GTBASE, GT_SCS3LD_OFS add REGHI, GTBASE, GT_SCS3HD_OFS jal setup_dev_decode nop move v0, zero addu v1, BSIZE0, BSIZE1error_sdram: jr RA nop#undef RA#undef FREQ#undef BSIZE0#undef BSIZE1#undef GTBASE#undef ACCUM#undef DEV_BANKS#undef DEV_SIZE#undef PARITY_SUPPORT END(gt64120_configure_sdram) /************************************************************************ * * gt64120_setup_decode * Description : * ------------- * * Setup GT64120 memory decoding (except for SDRAM). * * Parameters : * ------------ * * a0 = PCI memory space base * a1 = PCI memory space size * a2 = PCI I/O space base * a3 = PCI I/O space size * t0 = CBUS base * t1 = CBUS size * t2 = Base address to be used for access to North Bridge registers. * * Return values : * --------------- * * 0 : No error. * ERROR_NB_DECODE : Illegal ranges requested. * ************************************************************************/SLEAF(gt64120_setup_decode)#define RA s0#define PCIMEM_BASE s1#define PCIMEM_SIZE s2#define PCIIO_BASE s3#define PCIIO_SIZE s4#define CBUS_BASE s5#define CBUS_SIZE s6#define GTBASE s7 move RA, ra move PCIMEM_BASE, a0 move PCIMEM_SIZE, a1 move PCIIO_BASE, a2 move PCIIO_SIZE, a3 move CBUS_BASE, t0 move CBUS_SIZE, t1 move GTBASE, t2 /**** PCI0_MEM0 ****/ /* Adjust the banksize to that it is contained within * a 256MB block (addr[31:28] constant). */ move LO, PCIMEM_BASE srl t0, LO, 28 /* t0 = LO[31:28] */ addu HI, LO, PCIMEM_SIZE /* HI address before adjust */ subu t1, HI, 1 srl t1, 28 /* t1 = (HI-1)[31:28] */ beq t0, t1, 1f nop /* We crossed a 256MB boundary. Limit HI to boundary address */ addu t0, 1 sll HI, t0, 281: /* Adjust the banksize so that it allows PCI IO to * be present as a "red page" in the middle. */ sltu t0, PCIIO_BASE, HI beq t0, zero, 3f nop move HI, PCIIO_BASE3: /* Store HI since we will need it for PCI0_MEM1 */ move t3, HI /* Setup decode */ add REGLO, GTBASE, GT_PCI0M0LD_OFS add REGHI, GTBASE, GT_PCI0M0HD_OFS jal setup_cpu_decode /* Modifies t0..t2 */ nop bne v0, zero, error_decode nop /* Calc whether PCI memory was covered by PCI0_MEM0 */ addu HI, PCIMEM_BASE, PCIMEM_SIZE bne HI, t3, setup_mem1 move LO, t3 /* We don't need PCI0_MEM1, so disable it */ move HI, zerosetup_mem1: /**** PCI0_MEM1 ****/ /* Adjust the bankstart so that it does not interfeer with PCI IO */ add t1, PCIIO_BASE, PCIIO_SIZE sltu t0, LO, t1 beq t0, zero, 1f nop move LO, t11: add REGLO, GTBASE, GT_PCI0M1LD_OFS add REGHI, GTBASE, GT_PCI0M1HD_OFS jal setup_cpu_decode nop bne v0, zero, error_decode nopsetup_io: /**** PCI0_IO ****/ move LO, PCIIO_BASE addu HI, LO, PCIIO_SIZE add REGLO, GTBASE, GT_PCI0IOLD_OFS add REGHI, GTBASE, GT_PCI0IOHD_OFS jal setup_cpu_decode nop bne v0, zero, error_decode nop /**** PCI1 (not used) ****/ move HI, zero add REGLO, GTBASE, GT_PCI1M0LD_OFS add REGHI, GTBASE, GT_PCI1M0HD_OFS jal setup_cpu_decode nop add REGLO, GTBASE, GT_PCI1M1LD_OFS add REGHI, GTBASE, GT_PCI1M1HD_OFS jal setup_cpu_decode nop add REGLO, GTBASE, GT_PCI1IOLD_OFS add REGHI, GTBASE, GT_PCI1IOHD_OFS jal setup_cpu_decode nop /**** CS[2:0] ****/ move LO, CBUS_BASE add HI, LO, CBUS_SIZE add REGLO, GTBASE, GT_CS20LD_OFS add REGHI, GTBASE, GT_CS20HD_OFS jal setup_cpu_decode nop bne v0, zero, error_decode nop /* CS0 */ add REGLO, GTBASE, GT_CS0LD_OFS add REGHI, GTBASE, GT_CS0HD_OFS jal setup_dev_decode nop /* CS1, CS2 (not used) */ move HI, zero add REGLO, GTBASE, GT_CS1LD_OFS add REGHI, GTBASE, GT_CS1HD_OFS jal setup_dev_decode nop add REGLO, GTBASE, GT_CS2LD_OFS add REGHI, GTBASE, GT_CS2HD_OFS jal setup_dev_decode nop /**** Done, return to caller ****/done: move v0, zeroerror_decode : jr RA nop#undef RA#undef PCIMEM_BASE#undef PCIMEM_SIZE#undef PCIIO_BASE#undef PCIIO_SIZE#undef CBUS_BASE#undef CBUS_SIZE#undef GTBASEEND(gt64120_setup_decode)/************************************************************************ * * gt64120_remap_pci_io * Description : * ------------- * * Remap PCI IO range so that PCI IO range starts at address 0 on * PCI (NB no longer transparent for PCI IO). * * Parameters : * ------------ * * a0 = Base address to be used for access to North Bridge registers. * * Return values : * --------------- * * None * ************************************************************************/SLEAF(gt64120_remap_pci_io) sw zero, GT_PCI0IORMP_OFS(a0) jr ra nopEND(gt64120_remap_pci_io)/************************************************************************ * Implementation : Static functions ************************************************************************//* Functions for setup of GT64120 cpu/device decoder * * Input parameters : * ------------------ * LO (a0) = lo address * HI (a1) = high address * REGLO (a2) = lo register * REGHI (a3) = high register *//************************************************************************ * setup_cpu_decode ************************************************************************/SLEAF(setup_cpu_decode) /* Check that LO and HI addresses are 2MB aligned (LO[20:0] == 0) */ li t0, MSK(21) and t0, LO bne t0, zero, error_cpu_decode nop /* Check that LO and HI are in the same 256 MB block * ((HI-1)[31:28] == LO[31:28]) * * Unless HI = 0 indicating that range should be disabled. */ beq HI, zero, 1f nop srl t0, LO, 28 subu t1, HI, 1 srl t1, 28 bne t0, t1, error_cpu_decode nop1: b setup_decode li t0, 21error_cpu_decode : li v0, ERROR_NB_DECODE jr ra nopEND(setup_cpu_decode)/************************************************************************ * setup_dev_decode ************************************************************************/SLEAF(setup_dev_decode) b setup_decode li t0, 20END(setup_dev_decode) /************************************************************************ * setup_decode ************************************************************************/SLEAF(setup_decode) bne HI, zero, 1f nop li t1, 0xFFFF b 2f move t2, zero 1: srlv t1, LO, t0 subu t2, HI, 1 srlv t2, t2, t02: GT_SW( t1, 0, REGLO ) GT_SW( t2, 0, REGHI ) jr ra move v0, zeroEND(setup_decode)⌨️ 快捷键说明
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