📄 bonito64_core.s
字号:
END(bonito64_get_pcimem_base)/************************************************************************ * * bonito64_config_write * Description : * ------------- * * Perform 32 bit PCI configuration write cycle on local bus. * * Parameters : * ------------ * * a0 = device number (function 0 assumed) * a1 = register * a2 = data * a3 = Base address to be used for access to North Bridge registers. * (a3 is ignored since this is not configurable for Bonito64) * * Return values : * --------------- * * v0 = 0 if OK * v0 = ERROR_NB_CONFIG_WRITE if not OK * ************************************************************************/SLEAF(bonito64_config_write) /* Clear master/slave aborts */ li t3, KSEG1(BONITO_REG_BASE) lw t1, BONITO_PCICMD(t3) li t2, BONITO_PCICMD_MABORT_CLR | BONITO_PCICMD_MTABORT_CLR or t1, t2 sw t1, BONITO_PCICMD(t3) /* Setup pattern to be used as PCI "address" for Type 0 cycle */ /* IDSEL */ addu t2, a0, PCI_DEVNUM2IDSEL_OFFSET li t1, 1 sllv t1, t1, t2 /* Register number */ or t1, a1 /* t1 now holds pattern */ /* Setup pcimap_cfg */ srl t2, t1, 16 sw t2, BONITO_PCIMAP_CFG(t3) /* Flush Bonito register block */ lw t2, BONITO_PCIMAP_CFG(t3) sync /* Perform access */ and t2, t1, 0xFFFF li t1, KSEG1(BONITO_PCICFG_BASE) addu t1, t2 sw a2, 0(t1) /* Wait till done */1: lw t1, BONITO_PCIMSTAT(t3) andi t1, 0xF bne t1, zero, 1b nop /* Detect master/slave abort */ lw t1, BONITO_PCICMD(t3) li t2, BONITO_PCICMD_MABORT_CLR | BONITO_PCICMD_MTABORT_CLR and t1, t2 beq t1, zero, 1f move v0, zero li v0, ERROR_NB_CONFIG_WRITE1: jr ra nopEND(bonito64_config_write)/************************************************************************ * * bonito64_configure_sdram * Description : * ------------- * * Setup Bonito64 SDRAM configuration * * Parameters : * ------------ * * a0 = Worst case (lowest) bus freq. (MHz) for setting timing parms. * a1 = Base address to be used for access to North Bridge registers. * a2 = Max SDRAM size supported by platform. * (a1, a2 are ignored since this is not configurable for Bonito64) * * a3 = 0 => CoreBonito64 * a3 = 1 => Core20K * * Return values : * --------------- * * v0 = error code (0 = OK) * v1 = RAM size * ************************************************************************/SLEAF(bonito64_configure_sdram)#define RA s0#define MOD_BANKS s1#define BSIZE0 s2#define BSIZE1 s3#define ACCUM s4 move RA, ra /* Check module width */ li a0, SPD_MODULE_WIDTH_LO jal sys_spd_read nop bne v0, zero, error_bonito64_configure_sdram li a0, 64 bne v1, a0, error_bonito64_configure_sdram li v0, ERROR_SDRAM_WIDTH li a0, SPD_MODULE_WIDTH_HI jal sys_spd_read nop bne v0, zero, error_bonito64_configure_sdram li a0, 0 bne v1, a0, error_bonito64_configure_sdram li v0, ERROR_SDRAM_WIDTH /**** Setup SDRAM configuration ****/ /* Misc parameters */ li ACCUM, BONITO_SDCFG_AWIDTH64 | BONITO_SDCFG_BABSENT |\ BONITO_SDCFG_EXTPRECH |\ BONITO_SDCFG_EXTRASCAS /* Rows */ li a0, SPD_ROWS jal sys_spd_read nop bne v0, zero, error_bonito64_configure_sdram nop and v1, SPD_ROWS_A_MSK srl v1, SPD_ROWS_A_SHF subu v1, 11 sll v1, BONITO_SDCFG_AROWBITS_SHIFT or ACCUM, v1 /* Columns */ li a0, SPD_COL jal sys_spd_read nop bne v0, zero, error_bonito64_configure_sdram nop and v1, SPD_COL_A_MSK srl v1, SPD_COL_A_SHF subu v1, 8 sll v1, v1, BONITO_SDCFG_ACOLBITS_SHIFT or ACCUM, v1 /* Device banks */ li a0, SPD_DEVICE_BANKS jal sys_spd_read nop bne v0, zero, error_bonito64_configure_sdram nop li a0, 1 beq a0, v1, 1f nop /* 2 device banks */ or ACCUM, BONITO_SDCFG_ABANKBIT1: /* Module banks (aka sides) */ li a0, SPD_MODULE_BANKS jal sys_spd_read nop bne v0, zero, error_bonito64_configure_sdram nop move MOD_BANKS, v1 li a0, 1 beq a0, MOD_BANKS, 1f nop /* 2 sides */ or ACCUM, BONITO_SDCFG_ASIDES1: /* Size of Bank(s) */ li a0, SPD_ROW_DENSITY jal sys_spd_read nop bne v0, zero, error_bonito64_configure_sdram nop /* bank 0 */ li BSIZE0, 512*1024*10241: and t0, v1, 1 << 7 bne t0, zero, 2f sll v1, 1 b 1b srl BSIZE0, 12: /* bank 1 (if available) */ li t0, 1 beq MOD_BANKS, t0, 2f /* 1 bank only */ move BSIZE1, zero and v1, 0xFF bne v1, zero, error_bonito64_configure_sdram li v0, ERROR_SDRAM_MOD_BANKS /* 2 asymmetrical banks. Not supported by Bonito64 */ move BSIZE1, BSIZE0 /* 2 symmetrical banks */2: /* Validate that memory size <= BONITO_PCILO_BASE * (BONITO_PCILO_BASE is first address not used for RAM) */ addu t0, BSIZE1, BSIZE0 li t1, BONITO_PCILO_BASE sltu t0, t1, t0 bne t0, zero, error_bonito64_configure_sdram li v0, ERROR_SDRAM_SIZE1: /* CAS latency */ li a0, SPD_CASLAT jal sys_spd_read nop bne v0, zero, error_bonito64_configure_sdram nop and t0, v1, SPD_CASLAT_2_BIT bne t0, zero, 1f nop /* CAS latency 2 not supported, so use CAS latency 3 */ li t0, BONITO_SDCFG_EXTRDDATA or ACCUM, t01: /* Refresh rate */ li a0, SPD_RFSH_RT jal sys_spd_read nop bne v0, zero, error_bonito64_configure_sdram nop and v1, SPD_RFSH_RT_RATE_MSK srl v1, SPD_RFSH_RT_RATE_SHF li t0, SPD_RFSH_RT_RATE_3_9 /* 3.9 us */ beq t0, v1, set_rfsh li t0, 0 /* x1 */ li t0, SPD_RFSH_RT_RATE_7_8 /* 7.8 us */ beq t0, v1, set_rfsh li t0, 1 /* x2 */ li t0, SPD_RFSH_RT_RATE_15_625 /* 15.625 us */ beq t0, v1, set_rfsh li t0, 2 /* x4 */ /* assume 31.3us */ li t0, 3 /* x8 */set_rfsh : sll t0, BONITO_SDCFG_DRAMRFSHMULT_SHIFT or ACCUM, t0 /* Determine Parity support */ li a0, SPD_CONFIG_TYPE jal sys_spd_read nop bne v0, zero, error_bonito64_configure_sdram nop li t0, SPD_CONFIG_TYPE_PARITY beq t0, v1, parity_support nop li t0, SPD_CONFIG_TYPE_ECC beq t0, v1, error_bonito64_configure_sdram li v0, ERROR_SDRAM_ERRORCHECK b no_parity_support nopparity_support: li t0, BONITO_SDCFG_DRAMPARITY or ACCUM, t0no_parity_support: /* Core20K (ie 20Kc CPU) vs CoreBonito64 (ie QED CPU) */ beq a3, zero, 1f nop /* Core20K */ li t0, (2 << BONITO_SDCFG_DRAMBURSTLEN_SHIFT) b 2f nop1: /* CoreBonito64 */ li t0, (3 << BONITO_SDCFG_DRAMBURSTLEN_SHIFT)2: or ACCUM, t0 /* Store setup in bonito sdram configuration register */ jal bonito64_write_sdcfg move a0, ACCUM /* Set return parameters */ move v0, zero /* No error */ addu v1, BSIZE0, BSIZE1 /* memory size */ error_bonito64_configure_sdram: /* Done */ jr RA nop#undef RA#undef MOD_BANKS#undef BSIZE0#undef BSIZE1#undef ACCUM END(bonito64_configure_sdram) /************************************************************************ * * bonito64_setup_decode * Description : * ------------- * * Setup Bonito64 memory decoding (except for SDRAM). * * Parameters : * ------------ * * a0 = PCI memory space base * a1 = PCI memory space size * a2 = PCI I/O space base * a3 = PCI I/O space size * t0 = CBUS base * t1 = CBUS size * t2 = Base address to be used for access to North Bridge registers. * (t2 is ignored since this is not configurable for Bonito64) * * Return values : * --------------- * * Always 0 * ************************************************************************/SLEAF(bonito64_setup_decode) jr ra move v0, zeroEND(bonito64_setup_decode)/************************************************************************ * * bonito64_remap_pci_io * Description : * ------------- * * Remap PCI IO range so that PCI IO range starts at address 0 on * PCI (NB no longer transparent for PCI IO). * * Parameters : * ------------ * * a0 = Base address to be used for access to North Bridge registers. * (a0 is ignored since this is not configurable for Bonito64) * * Return values : * --------------- * * None * ************************************************************************/SLEAF(bonito64_remap_pci_io) jr ra move v0, zeroEND(bonito64_remap_pci_io)⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -