cache_cpu.s

MIPS YAMON, a famous monitor inc. source, make file and PDF manuals.

	move	v0, zero

icache_lines_mips32:
	
	/* Read CONFIG1 register, which holds implementation data */
	MFC0_SEL_OPCODE( R_t9, R_C0_Config1, R_C0_SelConfig1 )

#define config1	t9

	/* I-cache lines
	 * Calculated as associativity * sets per way
	 */
	li	t8, M_Config1IA
	and	t8, config1
	li	t7, S_Config1IA
	srl	t8, t7
	addiu	t8,1				/* t8 = associativity	*/

	li	t7, M_Config1IS
	and	t7, config1
	li	t9, S_Config1IS
	srl	t7, t9
	li	t9, 0x40
	sll	t7, t9, t7			/* t7 = sets per way	*/

	multu	t8, t7
	mflo    v0

	jr	ra
	nop

icache_lines_qed_rm5261:
	li	v0, (QED_RM5261_ICACHE_SIZE / QED_RM5261_ICACHE_LSIZE)
	jr	ra
	nop

icache_lines_qed_rm7061a:
	li	v0, (QED_RM7061A_ICACHE_SIZE / QED_RM7061A_ICACHE_LSIZE)
	jr	ra
	nop

END(sys_determine_icache_lines_flash)


/************************************************************************
 *
 *                          sys_determine_icache_assoc_flash
 *  Note :
 *  ------
 *  This routine is called also from syscon.c
 *  and must obey c calling conventions - and cannot use k0/k1
 *
 *  Description :
 *  -------------
 *  Determine ICACHE associativity
 *
 *  input : a0 = processor ID
 *	
 *  Return values :
 *  ---------------
 *  v0 = ICACHE associativity
 *
 ************************************************************************/
LEAF(sys_determine_icache_assoc_flash)	

	/* Check if it is a MIPS32/64 processor */	
	srl	t9, a0, S_PRIdCoID
	and     t9, M_PRIdCoID >> S_PRIdCoID
	li	t8, C0_PRID_COMP_NOT_MIPS32_64
	bne	t9, t8, icache_assoc_mips32
	nop
	/* Not a MIPS32/64 processor */
	li	t9, QED_RM52XX
	beq	a0, t9, icache_assoc_qed_rm5261
	nop
	li	t9, QED_RM70XX
	beq	a0, t9, icache_assoc_qed_rm7061a
	nop
	/* Unknown CPU */
icache_assoc_zero:
	jr	ra
	move	v0, zero

icache_assoc_mips32:
	
	/* Read CONFIG1 register, which holds implementation data */
	MFC0_SEL_OPCODE( R_t9, R_C0_Config1, R_C0_SelConfig1 )

#define config1	t9

	/* I-cache associativity */
	li	t8, M_Config1IA
	and	t8, config1
	li	t7, S_Config1IA
	srl	t8, t7
	addiu	v0,t8,1				/* t8 = associativity	*/
	jr	ra
	nop

icache_assoc_qed_rm5261:
	li	v0, QED_RM5261_ICACHE_ASSOC
	jr	ra
	nop

icache_assoc_qed_rm7061a:
	li	v0, QED_RM7061A_ICACHE_ASSOC
	jr	ra
	nop

END(sys_determine_icache_assoc_flash)


/************************************************************************
 *
 *                          sys_determine_dcache_linesize_flash
 *  Note :
 *  ------
 *  This routine is called also from syscon.c
 *  and must obey c calling conventions - and cannot use k0/k1
 *
 *  Description :
 *  -------------
 *  Determine DCACHE linesize
 *
 *  input : a0 = processor ID
 *	
 *  Return values :
 *  ---------------
 *  v0 = DCACHE linesize in bytes
 *
 ************************************************************************/
LEAF(sys_determine_dcache_linesize_flash)	

	/* Check if it is a MIPS32/64 processor */	
	srl	t9, a0, S_PRIdCoID
	and     t9, M_PRIdCoID >> S_PRIdCoID
	li	t8, C0_PRID_COMP_NOT_MIPS32_64
	bne	t9, t8, dcache_linesize_mips32
	nop
	/* Not a MIPS32/64 processor */
	li	t9, QED_RM52XX
	beq	a0, t9, dcache_linesize_qed_rm5261
	nop
	li	t9, QED_RM70XX
	beq	a0, t9, dcache_linesize_qed_rm7061a
	nop
	/* Unknown CPU */
dcache_linesize_zero:
	jr	ra
	move	v0, zero

dcache_linesize_mips32:
	
	/* Read CONFIG1 register, which holds implementation data */
	MFC0_SEL_OPCODE( R_t9, R_C0_Config1, R_C0_SelConfig1 )

#define config1	t9

	/* D-cache line size */
	li	t8, M_Config1DL
	and	t8, config1
	beq	t8, zero, dcache_linesize_zero
	li	t7, S_Config1DL
	srl	t8, t7
	li	t7, 0x2
	sll	v0, t7, t8

	jr	ra
	nop

dcache_linesize_qed_rm5261:
	li	v0, QED_RM5261_DCACHE_LSIZE
	jr	ra
	nop

dcache_linesize_qed_rm7061a:
	li	v0, QED_RM7061A_DCACHE_LSIZE
	jr	ra
	nop

END(sys_determine_dcache_linesize_flash)	


/************************************************************************
 *
 *                          sys_determine_dcache_lines_flash
 *  Note :
 *  ------
 *  This routine is called also from syscon.c
 *  and must obey c calling conventions - and cannot use k0/k1
 *
 *  Description :
 *  -------------
 *  Determine number of DCACHE lines
 *
 *  input : a0 = processor ID
 *	
 *  Return values :
 *  ---------------
 *  v0 = number of DCACHE lines
 *
 ************************************************************************/
LEAF(sys_determine_dcache_lines_flash)	

	/* Check if it is a MIPS32/64 processor */	
	srl	t9, a0, S_PRIdCoID
	and     t9, M_PRIdCoID >> S_PRIdCoID
	li	t8, C0_PRID_COMP_NOT_MIPS32_64
	bne	t9, t8, dcache_lines_mips32
	nop
	/* Not a MIPS32/64 processor */
	li	t9, QED_RM52XX
	beq	a0, t9, dcache_lines_qed_rm5261
	nop
	li	t9, QED_RM70XX
	beq	a0, t9, dcache_lines_qed_rm7061a
	nop
	/* Unknown CPU */
dcache_lines_zero:
	jr	ra
	move	v0, zero

dcache_lines_mips32:
	
	/* Read CONFIG1 register, which holds implementation data */
	MFC0_SEL_OPCODE( R_t9, R_C0_Config1, R_C0_SelConfig1 )

#define config1	t9

	/* D-cache lines
	 * Calculated as associativity * sets per way
	 */
	li	t8, M_Config1DA
	and	t8, config1
	li	t7, S_Config1DA
	srl	t8, t7
	addiu	t8,1				/* t8 = associativity	*/

	li	t7, M_Config1DS
	and	t7, config1
	li	t9, S_Config1DS
	srl	t7, t9
	li	t9, 0x40
	sll	t7, t9, t7			/* t7 = sets per way	*/

	multu	t8, t7
	mflo    v0

	jr	ra
	nop

dcache_lines_qed_rm5261:
	li	v0, (QED_RM5261_DCACHE_SIZE / QED_RM5261_DCACHE_LSIZE)
	jr	ra
	nop

dcache_lines_qed_rm7061a:
	li	v0, (QED_RM7061A_DCACHE_SIZE / QED_RM7061A_DCACHE_LSIZE)
	jr	ra
	nop

END(sys_determine_dcache_lines_flash)


	
/************************************************************************
 *
 *                          sys_determine_dcache_assoc_flash
 *  Note :
 *  ------
 *  This routine is called also from syscon.c
 *  and must obey c calling conventions - and cannot use k0/k1
 *
 *  Description :
 *  -------------
 *  Determine DCACHE associativity
 *
 *  input : a0 = processor ID
 *	
 *  Return values :
 *  ---------------
 *  v0 = DCACHE associativity
 *
 ************************************************************************/
LEAF(sys_determine_dcache_assoc_flash)	

	/* Check if it is a MIPS32/64 processor */	
	srl	t9, a0, S_PRIdCoID
	and     t9, M_PRIdCoID >> S_PRIdCoID
	li	t8, C0_PRID_COMP_NOT_MIPS32_64
	bne	t9, t8, dcache_assoc_mips32
	nop
	/* Not a MIPS32/64 processor */
	li	t9, QED_RM52XX
	beq	a0, t9, dcache_assoc_qed_rm5261
	nop
	li	t9, QED_RM70XX
	beq	a0, t9, dcache_assoc_qed_rm7061a
	nop
	/* Unknown CPU */
dcache_assoc_zero:
	jr	ra
	move	v0, zero

dcache_assoc_mips32:
	
	/* Read CONFIG1 register, which holds implementation data */
	MFC0_SEL_OPCODE( R_t9, R_C0_Config1, R_C0_SelConfig1 )

#define config1	t9

	/* I-cache associativity */
	li	t8, M_Config1DA
	and	t8, config1
	li	t7, S_Config1DA
	srl	t8, t7
	addiu	v0,t8,1				/* t8 = associativity	*/
	jr	ra
	nop

dcache_assoc_qed_rm5261:
	li	v0, QED_RM5261_DCACHE_ASSOC
	jr	ra
	nop

dcache_assoc_qed_rm7061a:
	li	v0, QED_RM7061A_DCACHE_ASSOC
	jr	ra
	nop

END(sys_determine_dcache_assoc_flash)


/************************************************************************
 *
 *                          sys_init_l2cache_flash
 *
 *  Description :
 *  -------------
 *  Invalidate entire L2 CACHE
 *
 *  Inputs : a0 = cache size (bytes)
 *           a1 = line size  (bytes)
 *	     a2 = processor ID
 *	
 *  Return values :
 *  ---------------
 *  None
 *
 ************************************************************************/
LEAF( sys_init_l2cache_flash )

	li	t0, MIPS_25Kf
	beq	t0, a2, 1f
	nop

	MTC0(   zero, C0_TagLo )
	MTC0(   zero, C0_TagHi )

	b	2f
	nop
	
1:
	/* 25Kf */
	MTC0_SEL_OPCODE( R_zero, R_C0_L23TagLo, R_C0_SelL23TagLo )
	MTC0_SEL_OPCODE( R_zero, R_C0_L23TagHi, R_C0_SelL23TagHi )

2:		
	beq     a0, zero, 2f		 /* just in case cache size = 0 */

	/* Calc an address that will correspond to the first cache line */
	li	t0, KSEG0BASE
	addu	t1, t0, a0
	subu	t1, a1		/* t1 = last line */

	/* Loop through all lines, invalidating each of them */
1:	
SET_MIPS3()
	cache	SCACHE_INDEX_STORE_TAG, 0(t0)	/* clear tag */
SET_MIPS0()
	bne	t0, t1, 1b
	addu	t0, a1
2:	
	jr	ra
	nop

END( sys_init_l2cache_flash )

	
/************************************************************************
 *
 *                          sys_init_icache
 *  Note :
 *  ------
 *  This routine is called also from sys_cpu.c and syscon_cpu.c
 *  and must obey c calling conventions - and cannot use k0/k1
 *
 *  Description :
 *  -------------
 *  Invalidate entire ICACHE
 *
 *  Inputs : a0 = cache size (bytes)
 *           a1 = line size  (bytes)
 *	
 *  Return values :
 *  ---------------
 *  None
 *
 ************************************************************************/
LEAF( sys_init_icache )
	
#ifdef NO_CACHE

	jr	ra
	nop

#else
		
        /* Clear TagLo and  TagHi.
	 * Note : For 20Kc and 25Kf, we actually need to clear
	 *        ITagLo and ITagHi, but they have the same 
	 *        register numbers (and select fields) as TagLo, TagHi.
	 */
	MTC0(   zero, C0_TagLo )
	MTC0(   zero, C0_TagHi )
	
	beq   a0, zero, 2f		 /* just in case cache size = 0 */

	/* Calc an address that will correspond to the first cache line */
	li	a2, KSEG0BASE

	/* Calc an address that will correspond to the last cache line  */
	addu	a3, a2, a0
	subu    a3, a1

	/* Loop through all lines, invalidating each of them */
1:	
SET_MIPS3()
	cache	ICACHE_INDEX_STORE_TAG, 0(a2)	/* clear tag */
SET_MIPS0()
	bne	a2, a3, 1b
	addu	a2, a1
2:
	jr	ra
	nop

#endif
		
END( sys_init_icache )
		

/************************************************************************
 *
 *                          sys_init_dcache
 *  Note :
 *  ------
 *  This routine is called also from sys_cpu.c
 *  and must obey c calling conventions - and cannot use k0/k1
 *
 *  Description :
 *  -------------
 *  Invalidate entire ICACHE
 *
 *  Inputs : a0 = cache size (bytes)
 *           a1 = line size  (bytes)
 *           a2 = processor ID
 *	
 *  Return values :
 *  ---------------
 *  None
 *
 ************************************************************************/
LEAF( sys_init_dcache )

#ifdef NO_CACHE

	jr	ra
	nop

#else
		
	li    a3, MIPS_20Kc
	beq   a3, a2, 1f
	nop
	li    a3, MIPS_25Kf
	beq   a3, a2, 1f
	nop

	MTC0( zero, C0_TagLo )
	MTC0( zero, C0_TagHi )
	b     2f
	nop
1:	
	/* 20Kc/25Kf : Use DTagLo and DTagHi for data cache */
	MTC0_SEL_OPCODE( R_zero, R_C0_DTagLo, R_C0_SelDTagLo )
	MTC0_SEL_OPCODE( R_zero, R_C0_DTagHi, R_C0_SelDTagHi )
2:	
	beq   a0, zero, 2f		 /* just in case cache size = 0 */

	/* Calc an address that will correspond to the first cache line */
	li	a2, KSEG0BASE

	/* Calc an address that will correspond to the last cache line  */
	addu	a3, a2, a0
	subu    a3, a1

	/* Loop through all lines, invalidating each of them */
1:	
SET_MIPS3()
	cache	DCACHE_INDEX_STORE_TAG, 0(a2)	/* clear tag */
SET_MIPS0()
	bne	a2, a3, 1b
	addu	a2, a1
2:
	jr	ra
	nop

#endif
		
END( sys_init_dcache )
		
	

/************************************************************************
 *  Implementation : Static functions
 ************************************************************************/

	
/* Messages */

	.text
	
MSG( msg_cache,        "CACHE"   )
MSG( msg_init_l2cache, "L2CACHE" )
MSG( msg_init_icache,  "ICACHE"  )
MSG( msg_init_dcache,  "DCACHE"  )