msc01_core.s

MIPS YAMON, a famous monitor inc. source, make file and PDF manuals.

	or	ACCUM, (MSC01_MC_TIMPAR_TDPL_PC133 << MSC01_MC_TIMPAR_TDPL_SHF)
	sw	ACCUM, MSC01_MC_TIMPAR_OFS(MC_REGS)

	/********************************************
	** Set up SDRAM refresh time register
	*/
	jal	my_read_eeprom
	li	a0, SPD_RFSH_RT
	and	v0, SPD_RFSH_RT_RATE_MSK

	li	t0, SPD_RFSH_RT_RATE_125	/* 125 us */
	beq	t0, v0, 1f
	li	t0, 125
	li	t0, SPD_RFSH_RT_RATE_62_5	/* 62.5 us */
	beq	t0, v0, 1f
	li	t0, 62
	li	t0, SPD_RFSH_RT_RATE_31_3	/* 31.3 us */
	beq	t0, v0, 1f
	li	t0, 31
	li	t0, SPD_RFSH_RT_RATE_15_625	/* 15.6 us */
	beq	t0, v0, 1f
	li	t0, 15
	li	t0, SPD_RFSH_RT_RATE_7_8	/* 7.8 us */
	beq	t0, v0, 1f
	li	t0, 7
	li	t0, 3			/* assume 3.9 us */
1:
	multu	FREQ, t0
	mflo	t0

	/* Adjust for clock ratio. Exploit the values: */
	/*                1=1/1,  2=2/3,  3=1/2,  4=1/3,  5=1/4 */
	/* Decremented:   0=1/1,  1=2/3,  2=1/2,  3=1/3,  4=1/4 */
	lw	v0, MSC01_MC_HC_CLKRAT_OFS(MC_REGS)
	li	t1, 1
	beq	v0, t1, 2f /* branch taken for ratio 1/1 */
	sub	v0, t1
	bne	v0, t1, 1f /* branch taken for ratios 1/2, 1/3, 1/4 */
	nop
	add	t0, t0     /* ratio 2/3,  multiply by 2 */
	li	v0, 3
1:
	divu	t0, v0     /*             divide by v0 */
	mflo	t0
2:
	/* never go below a certain minimum count */
	sltiu	v0, t0, MSC01_MC_TREFRESH_TREF_MIN
	beq	v0, zero, 3f
	nop
	li	t0, MSC01_MC_TREFRESH_TREF_MIN
3:
	sw	t0, MSC01_MC_TREFRESH_OFS(MC_REGS)

	/********************************************
	** Set up PARITY register
        **  If SDRAM module supports parity or ECC, enable parity support.
        **  If SDRAM module does not support any of those, disable
        **  parity support.
	** On SEAD-2 parity must remain disabled because
	**  the SDRAM parity data pins are not connected.
        */
	li	t0, PRODUCT_SEAD2_ID
	beq	t0, k0, 1f
	li	t0, 0

        /* Read parity support */
        jal	my_read_eeprom
        li	a0, SPD_CONFIG_TYPE
        li	t0, SPD_CONFIG_TYPE_ECC
        beq	t0, v0, 2f
        li	t0, SPD_CONFIG_TYPE_PARITY
        bne	t0, v0, 1f
	li	t0, 0
2:
        li	t0, MSC01_MC_HC_PARITY_PARITY_BIT
1:
	sw	t0, MSC01_MC_HC_PARITY_OFS(MC_REGS)

	/********************************************
	** Initialize RAM through MC_INITCMD register
	*/

	/* set up v1 with CL aligned to suit the MRS command below */
	lw	v1, MSC01_MC_LATENCY_OFS(MC_REGS)
	and	v1, MSC01_MC_LATENCY_CL_MSK
	sll	v1, 4 - MSC01_MC_LATENCY_CL_SHF

#ifdef SYSCTRL_DDR_SUPPORT
	lw	t0, MSC01_MC_HC_DDR_OFS(MC_REGS)
	andi	t0, MSC01_MC_HC_DDR_DDR_BIT
	beq	t0, zero, 1f
	nop
	/* Dual data rate RAM */
	li	t0, 0x00070000;
	sw	t0, MSC01_MC_INITCMD_OFS(MC_REGS) /* NOP */
	li	t0, 0x00320400;
	sw	t0, MSC01_MC_INITCMD_OFS(MC_REGS) /* PAL */
#if 0 /* 66 MHz RAM clock frequency is the limit to disable/enable DLL */
	li	t0, 0x00301000
	sw	t0, MSC01_MC_INITCMD_OFS(MC_REGS) /* EMRS; enable DLL */
#else
	li	t0, 0x00301001
	sw	t0, MSC01_MC_INITCMD_OFS(MC_REGS) /* EMRS; disable DLL */
#endif
	li	t0, 0x00300121
	sw	t0, MSC01_MC_INITCMD_OFS(MC_REGS) /* MRS; reset DLL, CL=2,WT=linear,BL=2 */
	li	t0, 0x00320400
	sw	t0, MSC01_MC_INITCMD_OFS(MC_REGS) /* PAL */
	li	t0, 0x00910000
	sw	t0, MSC01_MC_INITCMD_OFS(MC_REGS) /* CBR */
	sw	t0, MSC01_MC_INITCMD_OFS(MC_REGS) /* CBR */

	li	t0, 0x00300001; /* MRS; WT=linear,BL=2, CL=? */
	or	t0, v1
	sw	t0, MSC01_MC_INITCMD_OFS(MC_REGS) /* MRS */

	/* Give DLL time to syncronize (200 ram clock cycles) */
	lw	v0, MSC01_MC_HC_CLKRAT_OFS(MC_REGS)
	sll	v0, 7
3:
	bne	v0, zero, 3b
	sub	v0, 1
	b	2f
	nop

1:
#endif
	/* Single data rate RAM */
	li	t0, 0x00070000;
	sw	t0, MSC01_MC_INITCMD_OFS(MC_REGS) /* NOP */
	li	t0, 0x00320400;
	sw	t0, MSC01_MC_INITCMD_OFS(MC_REGS) /* PAL */
	li	t0, 0x00910000;
	sw	t0, MSC01_MC_INITCMD_OFS(MC_REGS) /* CBR */
	sw	t0, MSC01_MC_INITCMD_OFS(MC_REGS) /* CBR */
	sw	t0, MSC01_MC_INITCMD_OFS(MC_REGS) /* CBR */
	sw	t0, MSC01_MC_INITCMD_OFS(MC_REGS) /* CBR */
	sw	t0, MSC01_MC_INITCMD_OFS(MC_REGS) /* CBR */
	sw	t0, MSC01_MC_INITCMD_OFS(MC_REGS) /* CBR */
	sw	t0, MSC01_MC_INITCMD_OFS(MC_REGS) /* CBR */
	sw	t0, MSC01_MC_INITCMD_OFS(MC_REGS) /* CBR */

	li	t0, 0x00300000; /* MRS; WT=linear,BL=1, CL=? */
	or	t0, v1
	sw	t0, MSC01_MC_INITCMD_OFS(MC_REGS) /* MRS */
2:

	/********************************************
	** Enable SDRAM
	*/
	li	t0, MSC01_MC_CTRLENA_ENA_BIT
	sw	t0, MSC01_MC_CTRLENA_OFS(MC_REGS)

	/********************************************
	** Another look for parity
	*/
	lw	t0, MSC01_MC_HC_PARITY_OFS(MC_REGS)
	and	t0, MSC01_MC_HC_PARITY_PARITY_BIT
	beq	t0, zero, 9f
	nop

	/********************************************
	** Parity is enabled, so all parity bytes
	** must be initialized by full data width
	** uncached writes to the whole sdram memory.
	*/
	DISP_STR( msg_pram_clr ) /* destroys t5, t6, t7, t8, t9, ra */

	li	t0, KSEG1BASE	/* start addr */
	or	t1, t0, RAMSIZE /* limit */

	/* The processor is assumed to be MIPS32/64 compatible */
	MFC0(   v0, C0_Config )
	and	v0, M_ConfigAT
	sub	v0, K_ConfigAT_MIPS32<<S_ConfigAT
	bne	v0, zero, 2f
	nop
	/* 32 bit CPU */
	sub	t0, 4
1:
	add	t0, 4
	bnel	t0, t1, 1b	/* does not store on limit addr */
	sw	zero, 0(t0)
	b	9f
	nop

	/* 64 bit CPU */
SET_MIPS3()
2:	sub	t0, 8
1:	add	t0, 8
	bnel	t0, t1, 1b
	sd	zero, 0(t0)
SET_MIPS0()
9:

	/********************************************
	** Return
	*/
	move	v1, RAMSIZE
	jr	RA
	li	v0, 0


config_error:
	li	v0, ERROR_SDRAM_CONFIG
error_sdram:
	jr	RA
	nop


/************************************************************
** local subroutine - check and adjust rows and columns
** Makes a master return in case of error.
** Changes t0 and v0
** Uses t2	
** Returns memory size in v0
*/
checkrows:
	/* ROWS below 11 is not supported */
	sltiu	t0, ROWS, 11
	bne	t0, zero, config_error
	nop

	/* COLUMNS below 8 is not supported */
	sltiu	t0, COLUMNS, 8
	bne	t0, zero, config_error
	nop

	/* ROWS above 13 is limited to 13 */
	sltiu	t0, ROWS, 13+1
	bne	t0, zero, 1f
	nop
	li	ROWS, 13
1:

	/* COLUMNS is limited to less than ROWS */
	sltu	t0, COLUMNS, ROWS
	bne	t0, zero, 1f
	nop
	addiu	COLUMNS, ROWS, -1
1:

	/* COLUMNS + ROWS must not exceed 25 */
	add	t0, COLUMNS, ROWS
	sltiu	t0, t0, 26
	bne	t0, zero, 1f
	nop
2:
	addiu	COLUMNS, COLUMNS, -1
1:

	add	t0, ROWS, COLUMNS
	add	t0, 2+3		/* 4 banks * 8 bytes */

#define BIU_REGS t2
	/* correct size for msc01 configured buswidth */
	li	BIU_REGS, MSC01_BIU_REG_BASE
	lw	v0, MSC01_SC_ID_OFS(BIU_REGS)
	and	v0, MSC01_SC_ID_ID_MSK
	srl	v0, MSC01_SC_ID_ID_SHF
	/* explicitly check for configurations that use 64 bit data buses */
	xor	v0, MSC01_ID_SC_EC64
	beqz	v0, 1f
	 xor    v0, MSC01_ID_SC_EC64^MSC01_ID_SC_MGB
	beqz	v0, 1f
	 xor    v0, MSC01_ID_SC_MGB^MSC01_ID_SC_MGBIIA36D64C0IO
	beqz	v0, 1f
	 xor    v0, MSC01_ID_SC_MGBIIA36D64C0IO^MSC01_ID_SC_OCP
	beqz	v0,1f
	 nop
	
	sub	t0, 1	/* can only access half of the 64bit memory */
1:
#undef BIU_REGS
	
	/* correct size for data width */
	lw	v0, MSC01_MC_HC_FMDW_OFS(MC_REGS) /* check data with */
	and	v0, MSC01_MC_HC_FMDW_FMDW_BIT
	bne	v0, zero, 1f
	li	v0, 1
	sub	t0, 1		/* FMDW_BIT=0  =>  half data width */
1:
	sll	v0, t0	/* return size in bytes */

	/* CoreSYS - limit ram size to max 256 Mbyte */
	li	t0, CORE_SYS_MEMORY_SIZE
	slt	t0, t0, v0
	bne	t0, zero, 2b
	nop

	jr	ra
	nop

/************************************************************
** local subroutine - read from spd eeprom.
** makes a master return in case of error.
** Requires MC_REGS to be defined and set up.
** Returns byte read in v0.
*/

my_read_eeprom:
	li	v0, PRODUCT_ATLASA_ID
	bne	v0, k0, 1f
	nop

	/* Atlas - the SAA9730 must be used as master */
	/* Changes a0, a1, at, t0, t1, t2, t3, t5, t6, t7, t8, t9, v0, v1, RA2 */
	move	RA2, ra
	jal	sys_spd_read
	nop
	bne	v0, zero, error_msc01_eeprom
	nop
	jr	RA2
	move	v0, v1
error_msc01_eeprom:
	jr	RA
	nop
1:
	/* Malta */
	/* Changes a0, v0. */
	/* Setup address: on CoreSystem always use Device Serial Address 0 */
	sw	a0, MSC01_MC_SPD_ADR_OFS(MC_REGS)
1:
	/* Poll for ready */
	lw	v0, MSC01_MC_SPD_DAT_OFS(MC_REGS)
	andi	a0, v0, MSC01_MC_SPD_DAT_BUSY_MSK
	bne	a0, zero, 1b
	nop

	/* Check read err flag */
	andi	a0, v0, MSC01_MC_SPD_DAT_RDERR_MSK
	beq	a0, zero, eeprom_done
	nop

	/* Error */
	jr	RA
	li	v0, ERROR_SPD

eeprom_done:
	jr	ra
	andi	v0, MSC01_MC_SPD_DAT_RDATA_MSK

#undef RA
#undef MC_REGS
#undef RAMSIZE
#undef CSNUM
#undef ROW
#undef ROWSB
#undef COLUMNS
#undef COLUMNSB
#undef FREQ
#undef RA2

END(msc01_configure_sdram)


/************************************************************************
 *
 *                          msc01_setup_decode
 *  Description :
 *  -------------
 *  Setup msc01 memory decoding (except for SDRAM)
 *   - already done for MSC01.
 *
 *  Parameters :
 *  ------------
 *  a0 = PCI memory space base
 *  a1 = PCI memory space size
 *  a2 = PCI I/O space base
 *  a3 = PCI I/O space size
 *  t0 = CBUS base
 *  t1 = CBUS size
 *  t2 = Base address to be used for access to North Bridge registers.
 *
 *  Return values :
 *  ---------------
 *  Always 0
 *
 ************************************************************************/
SLEAF(msc01_setup_decode)

	jr	ra
	move    v0, zero

END(msc01_setup_decode)


/************************************************************************
 *
 *                          msc01_remap_pci_io
 *  Description :
 *  -------------
 *  Remap PCI IO range so that PCI IO range starts at address 0 on
 *  PCI - already does for MSC01.
 *
 *  Return values :
 *  ---------------
 *  None
 *
 ************************************************************************/
SLEAF(msc01_remap_pci_io)

	jr	ra
	move    v0, zero

END(msc01_remap_pci_io)




/* Messages */

MSG( msg_pram_clr,   "PRAM_CLR" )