msc01_core.s

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	sw	zero, MSC01_PCI_HEAD10_OFS(PCI_REGS)

	sw	zero, MSC01_PCI_HEAD12_OFS(PCI_REGS)
	sw	zero, MSC01_PCI_HEAD13_OFS(PCI_REGS)
	sw	zero, MSC01_PCI_HEAD14_OFS(PCI_REGS)
	sw	zero, MSC01_PCI_HEAD15_OFS(PCI_REGS)

	/* Set up Command Register */
	li	t0, PCI_SC_CMD_FBB_BIT  | \
		    PCI_SC_CMD_SERR_BIT | \
		    PCI_SC_CMD_PERR_BIT | \
		    PCI_SC_CMD_MS_BIT   | \
		    PCI_SC_CMD_BM_BIT
	sw	t0, MSC01_PCI_HEAD1_OFS(PCI_REGS)

	/* Set up byte swap properties */
#ifdef EB
	li	t0, (MSC01_PCI_SWAP_IO_NOSWAP    <<MSC01_PCI_SWAP_IO_SHF) | \
		    (MSC01_PCI_SWAP_MEM_NOSWAP   <<MSC01_PCI_SWAP_MEM_SHF)| \
		    (MSC01_PCI_SWAP_BAR0_BYTESWAP<<MSC01_PCI_SWAP_BAR0_SHF);
#else
	li	t0, (MSC01_PCI_SWAP_IO_NOSWAP    <<MSC01_PCI_SWAP_IO_SHF) | \
		    (MSC01_PCI_SWAP_MEM_NOSWAP   <<MSC01_PCI_SWAP_MEM_SHF)| \
		    (MSC01_PCI_SWAP_BAR0_NOSWAP  <<MSC01_PCI_SWAP_BAR0_SHF);
#endif
	sw	t0, MSC01_PCI_SWAP_OFS(PCI_REGS)

	/* Enable PCI host bridge to respond to configuration cycles */
	lw	t0, MSC01_PCI_CFG_OFS(PCI_REGS)	/* preserve retry count */
	li	t1, MSC01_PCI_CFG_RA_BIT |	/* slave read ahead  */     \
		    MSC01_PCI_CFG_G_BIT  |	/* master gathering  */     \
		    MSC01_PCI_CFG_EN_BIT  	/* configuration cycles */
	or	t0, t1
	sw	t0, MSC01_PCI_CFG_OFS(PCI_REGS)
	sync

	/* Done */
	move	v0, zero
	jr	ra
	move	v1, zero
#undef PCI_REGS

END(msc01_init)


/************************************************************************
 *
 *                          msc01_get_pcimem_base
 *  Description :
 *  -------------
 *  Return base address for PCI memory cycles.
 *
 ************************************************************************/
SLEAF(msc01_get_pcimem_base)

	li	v0, CORE_SYS_PCIMEM_BASE
	jr	ra
	nop

END(msc01_get_pcimem_base)


/************************************************************************
 *
 *                          msc01_config_write
 *  Description :
 *  -------------
 *  Perform 32 bit PCI configuration write cycle on local bus.
 *
 *  Parameters :
 *  ------------
 *  a0 = device number (function 0 assumed)
 *  a1 = register
 *  a2 = data
 *  a3 = Base address to be used for access to North Bridge registers.
 *  (a0 is ignored since this is hard defined by core_sys.h)
 *
 *  Return values :
 *  ---------------
 *  v0 = 0 if OK
 *  v0 = ERROR_NB_CONFIG_WRITE if not OK
 *
 ************************************************************************/
SLEAF(msc01_config_write)

#define PCI_REGS		t2
	li	PCI_REGS, MSC01_PCI_REG_BASE
        /* Clear cause register bits */
	li	t0, MSC01_PCI_INTSTAT_MA_BIT | MSC01_PCI_INTSTAT_TA_BIT
	sw	t0, MSC01_PCI_INTSTAT_OFS(PCI_REGS)

        /* Setup address */
	sll	a0, MSC01_PCI_CFGADDR_DNUM_SHF
	and	a0, MSC01_PCI_CFGADDR_DNUM_MSK
	and	a1, MSC01_PCI_CFGADDR_RNUM_MSK
	or	a0, a1
	sw	a0, MSC01_PCI_CFGADDR_OFS(PCI_REGS)
	sync

	/* Write data */
        sw	a2, MSC01_PCI_CFGDATA_OFS(PCI_REGS)

	/* Detect master/slave abort */
	sync
	lw	t1, MSC01_PCI_INTSTAT_OFS(PCI_REGS)
	and	t1, t0
	beq	t1, zero, 1f
	move	v0, zero
	li	v0, ERROR_NB_CONFIG_WRITE
1:
	jr	ra
	nop
#undef PCI_REGS

END(msc01_config_write)


/************************************************************************
 *
 *                          msc01_configure_sdram
 *  Description :
 *  -------------
 *  Setup CoreSYS SDRAM configuration
 *
 *  Parameters :
 *  ------------
 *  a0 = Worst case (lowest) bus freq. (MHz) for setting timing parms.
 *  a1 = Base address to be used for access to North Bridge registers.
 *  a2 = Max SDRAM size supported by platform.
 *  (a1, a2 are ignored since this is not configured for CoreSYS)
 *       Max SDRAM size is defined by CORE_SYS_PCILO_BASE (256 Mbyte)
 *
 *  Return values :
 *  ---------------
 *  v0 = error code (0 = OK)
 *  v1 = RAM size
 *
 ************************************************************************/
SLEAF(msc01_configure_sdram)

#define RA		s0
#define FREQ		s1
#define MC_REGS		s2
#define RAMSIZE		s3
#define CSNUM           s4
#define ROWS		s5
#define COLUMNS		s6
#define RA2		s7
#define ROWSB		a2
#define COLUMNSB	a3

	move	RA,	     ra
	move	FREQ,	     a0
/* Worst case setup based on frequency assumptions */
#define GCLK_SCALE_WORST_CASE 200 /*		(CORESYS_MAX_FREQ_MHZ) */

	move	RA, ra

	/********************************************
	** Configure IIC controller
	*/
	li	MC_REGS, MSC01_MC_REG_BASE
	li	t1, GCLK_SCALE_WORST_CASE
	sw	t1, MSC01_MC_SPD_CFG_OFS(MC_REGS)

	/* Read and check basic RAM type */
	jal	my_read_eeprom
	li	a0, SPD_FUNDAMENTAL_TYPE
	lw	t1, MSC01_MC_HC_DDR_OFS(MC_REGS)
	/* This bit reflects JP3 */
	andi	t1, MSC01_MC_HC_DDR_DDR_BIT
#ifdef SYSCTRL_DDR_SUPPORT
	bne	t1, zero, 1f
	li	t0, SPD_FUNDAMENTAL_TYPE_DDR
#endif
	li	t0, SPD_FUNDAMENTAL_TYPE_SDR
1:
	bne	t0, v0, error_sdram
	li	v0, ERROR_SPD

	/* Read basic data width - must be 0x0040 or 0x0048 (parity byte) */
	jal	my_read_eeprom
	li      a0, SPD_MODULE_WIDTH_LO
	or	v0, 8
	li	a0, 64 | 8
	bne	v0, a0, error_sdram
	li	v0, ERROR_SDRAM_WIDTH

	jal	my_read_eeprom
	li      a0, SPD_MODULE_WIDTH_HI
	bne	v0, zero, error_sdram
	li	v0, ERROR_SDRAM_WIDTH

	/* Read number of DIMM banks (CSNUM) */
	jal	my_read_eeprom
	li	a0, SPD_MODULE_BANKS
	move	CSNUM, v0

	/* Read number of SDRAM banks */
	jal	my_read_eeprom
	li	a0, SPD_DEVICE_BANKS
	li	t1, 4
	bne	t1, v0, error_sdram
	li	v0, ERROR_SDRAM_DEV_BANKS

	/****************************************
	** Compute RAM size
	** and values for physical bank config
	*/
	/* Read number of row address bits */
	jal	my_read_eeprom
	li	a0, SPD_ROWS

	andi	ROWS, v0, SPD_ROWS_A_MSK
	srl	ROWS, SPD_ROWS_A_SHF
	andi	ROWSB, v0, SPD_ROWS_B_MSK
	srl	ROWSB, SPD_ROWS_B_SHF

	/* Read number of column address bits */
	jal	my_read_eeprom
	li	a0, SPD_COL
	andi	COLUMNS, v0, SPD_COL_A_MSK
	srl	COLUMNS, SPD_COL_A_SHF
	andi	COLUMNSB, v0, SPD_COL_B_MSK
	srl	COLUMNSB, SPD_COL_B_SHF

	/* Configure registers for physical bank 0 */
	/* Check and adjust rows, columns if necessary */
        /* The following defines do not survive my_read_eeprom! */
#define CONFIG0 a1
#define CONFIG1 v1

	jal	checkrows
	nop

	move	RAMSIZE, v0

	sll	CONFIG0, ROWS, MSC01_MC_CFGPBx_ROWW_SHF
	or	CONFIG0, COLUMNS

	li	t0, 1
	beq	t0, CSNUM, 3f
	li	CONFIG1, 0
	li	t0, CORE_SYS_MEMORY_SIZE
	beq	t0, RAMSIZE, 3f
	nop

	/* Check and adjust rows, columns if necessary */
	/* CoreSYS: This is the second and last bank */
	/*          and may be set up smaller        */
	beq	ROWSB, zero, 1f
	slt	v0, ROWSB, ROWS
	beq	v0, zero, 1f
	nop
	/* ROWSB exists and is less than ROWS */
	move	ROWS, ROWSB
1:
	beq	COLUMNSB, zero, 1f
	slt	v0, COLUMNSB, COLUMNS
	beq	v0, zero, 1f
	nop
	/* COLUMNSB exists and is less than COLUMNS */
	move	COLUMNS, COLUMNSB
1:
	jal	checkrows
	nop

	add	RAMSIZE, v0
	sll	CONFIG1, ROWS, MSC01_MC_CFGPBx_ROWW_SHF
	or	CONFIG1, COLUMNS
3:
	/********************************************
	** Here starts writing to mc registers
	** Disable SDRAM
	*/
	sw	zero, MSC01_MC_CTRLENA_OFS(MC_REGS)

	/********************************************
	** Configure registers for physical banks 0-3
	*/
	sw	CONFIG0, MSC01_MC_CFGPB0_OFS(MC_REGS)
	sw	CONFIG1, MSC01_MC_CFGPB1_OFS(MC_REGS)
	sw	zero,    MSC01_MC_CFGPB2_OFS(MC_REGS)
	sw	zero,    MSC01_MC_CFGPB3_OFS(MC_REGS)

#undef CONFIG0
#undef CONFIG1

	/********************************************
	** Set up LATENCY register
	*/
#define ACCUM a3
	/* Read CAS Latency */
	jal	my_read_eeprom
	li	a0, SPD_CASLAT
/*
 * Note:
 * The present implementation is meant for an FPGA solution running up to 30MHz.
 * In hardened silicon, running faster, two things must be considered:
 * - Cut off frequencies for the suported cache latencies.
 * - Half ddr cache latencies requiring CLKRAT of 1:2 or 1:4 to work properly
 */

#ifdef SYSCTRL_DDR_SUPPORT
	 /* If CAS latency 2 is supported, use 2 otherwise 3 */
	lw	t1, MSC01_MC_HC_DDR_OFS(MC_REGS)
	andi	t1, MSC01_MC_HC_DDR_DDR_BIT
	beq	t1, zero, 1f
	andi	a0, v0, SPD_DDRCASLAT_2_0_BIT
	bne	a0, zero, 2f
	li	ACCUM, (2 << MSC01_MC_LATENCY_CL_SHF)

	 /* Use cache latency 3 as default */
	b	2f
	li	ACCUM, (3 << MSC01_MC_LATENCY_CL_SHF)
1:
#endif
	 /* If CAS latency 2 is supported, use 2 otherwise 3 */
	andi	a0, v0, SPD_CASLAT_2_BIT
	bne	a0, zero, 2f
	li	ACCUM, (2 << MSC01_MC_LATENCY_CL_SHF)
	li	ACCUM, (3 << MSC01_MC_LATENCY_CL_SHF)
2:
	/* Read CS Latency */
	jal	my_read_eeprom
	li	a0, SPD_CSLAT
	/* We only support CS latencies 0 and 1 */
	and	v0, SPD_CSLAT_0_BIT | SPD_CSLAT_1_BIT
	beq	v0, zero, config_error
	srl	v0, 1
	sll	v0, MSC01_MC_LATENCY_CSL_SHF
	or	ACCUM, v0

	/* Read Write Latency */
	jal	my_read_eeprom
	li	a0, SPD_WRLAT
	/* We only support WR latencies 0 and 1 */
	and	v0, SPD_WRLAT_0_BIT | SPD_WRLAT_1_BIT
	beq	v0, zero, config_error
	srl	v0, 1
	sll	v0, MSC01_MC_LATENCY_WL_SHF
	or	ACCUM, v0

	sw	ACCUM, MSC01_MC_LATENCY_OFS(MC_REGS)

	/********************************************
	** Set up IOCTL register
	*/
	sw	zero, MSC01_MC_IOCTRL_OFS(MC_REGS)

	/********************************************
	** Set up SDRAM command timing register
	*/

	/* Read Precharge time */
	jal	my_read_eeprom
	li	a0, SPD_TRP
#ifdef SYSCTRL_DDR_SUPPORT
	lw	t1, MSC01_MC_HC_DDR_OFS(MC_REGS)
	andi	t1, MSC01_MC_HC_DDR_DDR_BIT
	bnel	t1, zero, 1f
	srl	v0, 2   /* DDR - quarters of nanoseconds */
1:
#endif
	srl	v0, 3   /* 8 ns ~ 1 cycle at 125 MHz */
	sltiu	t0, v0, MSC01_MC_TIMPAR_TRP_MIN
	bnel	t0, zero, 1f
	li	v0, MSC01_MC_TIMPAR_TRP_MIN
	sltiu   t0, v0, MSC01_MC_TIMPAR_TRP_MAX+1
	beql	t0, zero, 1f
	li	v0, MSC01_MC_TIMPAR_TRP_MAX
1:
	sll	v0, MSC01_MC_TIMPAR_TRP_SHF
	move	ACCUM, v0

	/* Read RowActive time */
	jal	my_read_eeprom
	li	a0, SPD_TRAS
#ifdef SYSCTRL_DDR_SUPPORT
	lw	t1, MSC01_MC_HC_DDR_OFS(MC_REGS)
	andi	t1, MSC01_MC_HC_DDR_DDR_BIT
	bnel	t1, zero, 1f
	srl	v0, 2   /* DDR - quaters of nanoseconds */
1:
#endif
	srl	v0, 3   /* 8 ns ~ 1 cycle at 125 MHz */
	sltiu	t0, v0, MSC01_MC_TIMPAR_TRAS_MIN
	bnel	t0, zero, 1f
	li	v0, MSC01_MC_TIMPAR_TRAS_MIN
	sltiu   t0, v0, MSC01_MC_TIMPAR_TRAS_MAX+1
	beql	t0, zero, 1f
	li	v0, MSC01_MC_TIMPAR_TRAS_MAX
1:
	sll	v0, MSC01_MC_TIMPAR_TRAS_SHF
	or	ACCUM, v0

	/* Read RowToColcmd time */
	jal	my_read_eeprom
	li	a0, SPD_TRCD
#ifdef SYSCTRL_DDR_SUPPORT
	lw	t1, MSC01_MC_HC_DDR_OFS(MC_REGS)
	andi	t1, MSC01_MC_HC_DDR_DDR_BIT
	bnel	t1, zero, 1f
	srl	v0, 2   /* DDR - quaters of nanoseconds */
1:
#endif
	srl	v0, 3   /* 8 ns ~ 1 cycle at 125 MHz */
	sltiu	t0, v0, MSC01_MC_TIMPAR_TRCD_MIN
	bnel	t0, zero, 1f
	li	v0, MSC01_MC_TIMPAR_TRCD_MIN
	sltiu   t0, v0, MSC01_MC_TIMPAR_TRCD_MAX+1
	beql	t0, zero, 1f
	li	v0, MSC01_MC_TIMPAR_TRCD_MAX
1:
	sll	v0, MSC01_MC_TIMPAR_TRCD_SHF
	or	ACCUM, v0