msc01_core.s

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/************************************************************************
 *
 *  msc01_core.S
 *
 *  MSC01 (Mips System Controller) specific functions
 *
 * ######################################################################
 *
 * mips_start_of_legal_notice
 * 
 * Copyright (c) 2004 MIPS Technologies, Inc. All rights reserved.
 *
 *
 * Unpublished rights (if any) reserved under the copyright laws of the
 * United States of America and other countries.
 *
 * This code is proprietary to MIPS Technologies, Inc. ("MIPS
 * Technologies"). Any copying, reproducing, modifying or use of this code
 * (in whole or in part) that is not expressly permitted in writing by MIPS
 * Technologies or an authorized third party is strictly prohibited. At a
 * minimum, this code is protected under unfair competition and copyright
 * laws. Violations thereof may result in criminal penalties and fines.
 *
 * MIPS Technologies reserves the right to change this code to improve
 * function, design or otherwise. MIPS Technologies does not assume any
 * liability arising out of the application or use of this code, or of any
 * error or omission in such code. Any warranties, whether express,
 * statutory, implied or otherwise, including but not limited to the implied
 * warranties of merchantability or fitness for a particular purpose, are
 * excluded. Except as expressly provided in any written license agreement
 * from MIPS Technologies or an authorized third party, the furnishing of
 * this code does not give recipient any license to any intellectual
 * property rights, including any patent rights, that cover this code.
 *
 * This code shall not be exported, reexported, transferred, or released,
 * directly or indirectly, in violation of the law of any country or
 * international law, regulation, treaty, Executive Order, statute,
 * amendments or supplements thereto. Should a conflict arise regarding the
 * export, reexport, transfer, or release of this code, the laws of the
 * United States of America shall be the governing law.
 *
 * This code constitutes one or more of the following: commercial computer
 * software, commercial computer software documentation or other commercial
 * items. If the user of this code, or any related documentation of any
 * kind, including related technical data or manuals, is an agency,
 * department, or other entity of the United States government
 * ("Government"), the use, duplication, reproduction, release,
 * modification, disclosure, or transfer of this code, or any related
 * documentation of any kind, is restricted in accordance with Federal
 * Acquisition Regulation 12.212 for civilian agencies and Defense Federal
 * Acquisition Regulation Supplement 227.7202 for military agencies. The use
 * of this code by the Government is further restricted in accordance with
 * the terms of the license agreement(s) and/or applicable contract terms
 * and conditions covering this code from MIPS Technologies or an authorized
 * third party.
 *
 *
 *
 * 
 * mips_end_of_legal_notice
 * 
 *
 ************************************************************************/

/************************************************************************
 *  Include files
 ************************************************************************/

#include <sysdefs.h>
#include <mips.h>
#include <init.h>
#include <spd.h>
#include <pci_api.h>
#include <pci.h>
#include <product.h>
#include <core_sys.h>

/************************************************************************
 *  Definitions
 ************************************************************************/

#define SYSCTRL_DDR_SUPPORT 1


/************************************************************************
 *  Compile time assertions
 ************************************************************************/

/* check that SIZES are power of two */

#define POW2CHECK(X) ((X) - (((((X)-1) ^ (X)) >> 1 ) + 1 ))

#if ( POW2CHECK(CORE_SYS_MEMORY_SIZE) )
.error "CORE_SYS_MEMORY_SIZE MUST BE A POWER OF 2"
#endif
#if ( POW2CHECK(CORE_SYS_PCIMEM_SIZE2N) )
.error "CORE_SYS_PCIMEM_SIZE2N MUST BE A POWER OF 2"
#endif
#if ( POW2CHECK(CORE_SYS_PCIIO_SIZE) )
.error "CORE_SYS_PCIIO_SIZE MUST BE A POWER OF 2"
#endif
#if ( POW2CHECK(CORE_SYS_IP1MEM_SIZE) )
.error "CORE_SYS_IP1MEM_SIZE MUST BE A POWER OF 2"
#endif
#if ( POW2CHECK(CORE_SYS_REG_SIZE) )
.error "CORE_SYS_REG_SIZE MUST BE A POWER OF 2"
#endif
#if ( POW2CHECK(CORE_SYS_PBCMEM_SIZE) )
.error "CORE_SYS_PBCMEM_SIZE MUST BE A POWER OF 2"
#endif

/* check that SIZES are aligned properly */

#if (  (CORE_SYS_MEMORY_SIZE-1) & CORE_SYS_MEMORY_BASE )
.error "CORE_SYS_MEMORY_SIZE NOT ALIGNED PROPERLY"
#endif
#if (  (CORE_SYS_PCIMEM_SIZE2N-1) & CORE_SYS_PCIMEM_BASE )
.error "CORE_SYS_PCIMEM_SIZE2N NOT ALIGNED PROPERLY"
#endif
#if (  (CORE_SYS_PCIIO_SIZE-1) & CORE_SYS_PCIIO_BASE )
.error "CORE_SYS_PCIIO_SIZE NOT ALIGNED PROPERLY"
#endif
#if (  (CORE_SYS_IP1MEM_SIZE-1) & CORE_SYS_IP1MEM_BASE )
.error "CORE_SYS_IP1MEM_SIZE NOT ALIGNED PROPERLY"
#endif
#if (  (CORE_SYS_REG_SIZE-1) & CORE_SYS_REG_BASE )
.error "CORE_SYS_REG_SIZE NOT ALIGNED PROPERLY"
#endif
#if (  (CORE_SYS_PBCMEM_SIZE-1) & CORE_SYS_PBCMEM_BASE )
.error "CORE_SYS_PBCMEM_SIZE NOT ALIGNED PROPERLY"
#endif

/************************************************************************
 *  Public variables
 ************************************************************************/

/************************************************************************
 *  Static variables
 ************************************************************************/

/************************************************************************
 *  Implementation : Public functions
 ************************************************************************/

	.set noreorder


/************************************************************************	
 *		access_msc01
 *	Common function calling conventions, see init_core.S
 ************************************************************************/

LEAF( access_msc01 )
	
        li      t8, FUNC_INIT
	beq     t9, t8, msc01_init
	nop

        li      t8, FUNC_GET_PCIMEM_BASE
	beq     t9, t8, msc01_get_pcimem_base
	nop

        li      t8, FUNC_CONFIG_WRITE
	beq     t9, t8, msc01_config_write
	nop

        li      t8, FUNC_CONFIGURE_SDRAM
	beq     t9, t8, msc01_configure_sdram
	nop

        li      t8, FUNC_SETUP_DECODE
	beq     t9, t8, msc01_setup_decode
	nop

        /* FUNC_REMAP_PCI_IO */
	j	msc01_remap_pci_io
	nop

END( access_msc01 )


/************************************************************************
 *  Implementation : Static functions
 ************************************************************************/



/************************************************************************
 *
 *                          msc01_init
 *  Description :
 *  -------------
 *  Initialise msc01 just enough so that we can access PCI.
 *
 *  Parameters :
 *  ------------
 *  a0 = Base address to be used for access to North Bridge registers.
 *  (a0 is ignored since this is hard defined by core_sys.h)
 *
 *  Return values :
 *  ---------------
 *  v0 = error code (0 = OK)
 *  v1 = 1 -> Request software reset
 *
 ************************************************************************/
SLEAF(msc01_init)

        /*  We need to determine if we arrived here due to either :
	 *
	 *  1) A hardware or software reset.
	 *  2) Due to a "go bfc00000" command or under EJTAG control.
	 *
	 *  In case 2, we issue a software reset. We need to do
	 *  this since some devices will not otherwise be properly
	 *  reset.
	 *
	 *  We detect case 2 by checking if the System Controller Basic
	 *  Register Base address has been moved away from its reset value.
	 *  This is NOT the case after a hardware or software reset,
	 *  but IS otherwise the case since it is set below.
	 */

#define BIU_REGS			t2
	/* Check msc01 reset value of basic address decode */
	li	BIU_REGS, MSC01_REGADDR_RESET + \
		          MSC01_REGSPACE_BIU * MSC01_REGADDR_SIZE
	lw	t1, MSC01_BIU_RBBASL_OFS(BIU_REGS)
	li	t0, PHYS(MSC01_REGADDR_RESET )		/* reset value */
	beq	t0, t1, 1f
	nop

	/* Request software reset */
	jr	ra
	li	v1, 1

1:
	/* Disable external sync cycles on 24K */
	MFC0(v0, C0_PRId)
	and	v0, M_PRIdImp
	srl	v0, S_PRIdImp
	xor	v0, K_PRIdImp_24K
	bnez	v0, 1f
	 nop
	
	/* Reset CONFIG7:bit8 to disable external sync cycles */
	MFC0_SEL_OPCODE(R_v0, 16, 7)
	and	v0,~(1<<8)
	MTC0_SEL_OPCODE( R_v0, 16, 7)
	
1:
	/* Move register block base address to 0x1bc00000 */
	/* Decrease size of IP3 space to avoid clash with reg-space */
	/* IP3 temporary decrease         - reset 0x18000000 */
	li	t0, -CORE_SYS_IP3MEM_SIZE		     /*-0x18400000 */
	sw	t0, MSC01_BIU_IP3MSK1L_OFS(BIU_REGS)
	/* Register block move            - reset 0x1f800000 */
	li	t0, CORE_SYS_REG_BASE      		     /* 0x1bc00000 */
	sw	t0, MSC01_BIU_RBBASL_OFS(BIU_REGS)           /*-0x1c000000 */
	sync
#undef BIU_REGS

#define PBC_REGS			t2
	/* Speed up peripheral bus controller with configuration: */
	/*       CDIV=1, WS=16, WSIDLE=3, ADM=0,                  */
	/*       CAT=1,  CDT=1, RAT=2,    RDT=0, WAT=2, WDT=0     */
	li	PBC_REGS, MSC01_PBC_REG_BASE
	li	t0, (   1<<MSC01_PBC_CLKCFG_SHF)
	sw	t0, MSC01_PBC_CLKCFG_OFS(PBC_REGS)
	li	t0, (   1<<MSC01_PBC_CS0TIM_CDT_SHF) | \
		    (   1<<MSC01_PBC_CS0TIM_CAT_SHF)
	sw	t0, MSC01_PBC_CS0TIM_OFS(PBC_REGS)
	li	t0, (   0<<MSC01_PBC_CS0RW_RDT_SHF) | \
		    (   2<<MSC01_PBC_CS0RW_RAT_SHF) | \
		    (   0<<MSC01_PBC_CS0RW_WDT_SHF) | \
		    (   2<<MSC01_PBC_CS0RW_WAT_SHF)
	sw	t0, MSC01_PBC_CS0RW_OFS(PBC_REGS)
	lw	t0, MSC01_PBC_CS0CFG_OFS(PBC_REGS) /* preserve DTYP */
	li	t1, MSC01_PBC_CS0CFG_DTYP_MSK
	and	t0, t1
	ori	t0, (   0<<MSC01_PBC_CS0CFG_ADM_SHF) | \
		    (   3<<MSC01_PBC_CS0CFG_WSIDLE_SHF) | \
		    (0x10<<MSC01_PBC_CS0CFG_WS_SHF)
	sw	t0, MSC01_PBC_CS0CFG_OFS(PBC_REGS) /* WS=16, WSIDLE=3, ADM=0 */
#undef PBC_REGS

#define BIU_REGS			t2
	/* Setup msc01 basic address decode */
	li	BIU_REGS, MSC01_BIU_REG_BASE
	li	t0, CORE_SYS_MEMORY_BASE		     /* 0x00000000 */
	li	t1, -CORE_SYS_MEMORY_SIZE		     /*-0x10000000 */
	sw	t0, MSC01_BIU_MCBAS1L_OFS(BIU_REGS)
	sw	t1, MSC01_BIU_MCMSK1L_OFS(BIU_REGS)
	sw	t0, MSC01_BIU_MCBAS2L_OFS(BIU_REGS)
	sw	t1, MSC01_BIU_MCMSK2L_OFS(BIU_REGS)

	/* IP3 Peripheral Bus Controller  - reset 0x18000000 */
	li	t0, CORE_SYS_PBCMEM_BASE		     /* 0x1c000000 */
	li	t1, -CORE_SYS_PBCMEM_SIZE		     /*-0x20000000 */
	sw	t0, MSC01_BIU_IP3BAS1L_OFS(BIU_REGS)
	sw	t1, MSC01_BIU_IP3MSK1L_OFS(BIU_REGS)
	sw	t0, MSC01_BIU_IP3BAS2L_OFS(BIU_REGS)
	sw	t1, MSC01_BIU_IP3MSK2L_OFS(BIU_REGS)

	/* Read msc01 version and compare t0 0x0100 */
	lw	t0, MSC01_SC_ID_OFS(BIU_REGS)
	and	t0, 0xffff
	xor	t0, 0x0100
	bne	t0, zero, 101f
	nop

	/* MSC01 version 01.00 */
	/* IP3 was done before IP2 to avoid clash 0x18000000 */
	/* IP1 not used                   - reset 0x10000000 */
	/* Must be done before IP2 to avoid clash 0x10000000 */
	li	t0, CORE_SYS_IP1MEM_BASE10		     /* 0x1b800000 */
	li	t1, -CORE_SYS_IP1MEM_SIZE		     /*-0x1bc00000 */
	sw	t1, MSC01_BIU_IP1MSK1L_OFS(BIU_REGS)
	sw	t0, MSC01_BIU_IP1BAS1L_OFS(BIU_REGS)
	sw	t1, MSC01_BIU_IP1MSK2L_OFS(BIU_REGS)
	sw	t0, MSC01_BIU_IP1BAS2L_OFS(BIU_REGS)

	/* IP2 PCI                        - reset 0x14000000 */
	li	t0, CORE_SYS_PCIMEM_BASE		     /* 0x10000000 */
	li	t1, -CORE_SYS_PCIMEM_SIZE10		     /*-0x18000000 */
	sw	t0, MSC01_BIU_IP2BAS1L_OFS(BIU_REGS)
	sw	t1, MSC01_BIU_IP2MSK1L_OFS(BIU_REGS)
	li	t0, CORE_SYS_PCIIO_BASE			     /* 0x1b000000 */
	li	t1, -CORE_SYS_PCIIO_SIZE		     /*-0x1b800000 */
	sw	t1, MSC01_BIU_IP2MSK2L_OFS(BIU_REGS)
	sw	t0, MSC01_BIU_IP2BAS2L_OFS(BIU_REGS)
#undef BIU_REGS

#define PCI_REGS		t2
	li	PCI_REGS, MSC01_PCI_REG_BASE

        /* Setup PCI_SC2PMEM (0x10000000-0x17ffffff transparent) */
	li	t0, CORE_SYS_PCIMEM_BASE
	sw	t0, MSC01_PCI_SC2PMBASL_OFS(PCI_REGS)
	sw	t0, MSC01_PCI_SC2PMMAPL_OFS(PCI_REGS)
	li	t0, (-CORE_SYS_PCIMEM_SIZE10) & MSC01_PCI_SC2PMMSKL_MSK_MSK
	sw	t0, MSC01_PCI_SC2PMMSKL_OFS(PCI_REGS)
#undef PCI_REGS

	b	200f
	nop

#define BIU_REGS		t2
101:
	/* MSC01 version 01.01 and later */
	/* no clashing - prioritized compare: REGS > MEM > IP1 > IP2 > IP3 */
	/*        and prioritized pci spaces: SC2PCIIO > SC2PCIMEM         */
	/* IP1 not used                   - reset 0x10000000 */
	li	t0, CORE_SYS_IP1MEM_BASE		     /* 0x1bc00000 */
	li	t1, -CORE_SYS_IP1MEM_SIZE		     /*-0x1c000000 */
	sw	t1, MSC01_BIU_IP1MSK1L_OFS(BIU_REGS)
	sw	t0, MSC01_BIU_IP1BAS1L_OFS(BIU_REGS)
	sw	t1, MSC01_BIU_IP1MSK2L_OFS(BIU_REGS)
	sw	t0, MSC01_BIU_IP1BAS2L_OFS(BIU_REGS)

	/* IP2 PCI                        - reset 0x14000000 */
	li	t0, CORE_SYS_IP2MEM_BASE1		     /* 0x10000000 */
	li	t1, -CORE_SYS_IP2MEM_SIZE1		     /*-0x18000000 */
	sw	t0, MSC01_BIU_IP2BAS1L_OFS(BIU_REGS)
	sw	t1, MSC01_BIU_IP2MSK1L_OFS(BIU_REGS)
	li	t0, CORE_SYS_IP2MEM_BASE2		     /* 0x18000000 */
	li	t1, -CORE_SYS_IP2MEM_SIZE2		     /*-0x1c000000 */
	sw	t1, MSC01_BIU_IP2MSK2L_OFS(BIU_REGS)
	sw	t0, MSC01_BIU_IP2BAS2L_OFS(BIU_REGS)
#undef BIU_REGS

#define PCI_REGS		t2
	li	PCI_REGS, MSC01_PCI_REG_BASE

        /* Setup PCI_SC2PMEM (0x10000000-0x1fffffff transparent) */
	li	t0, CORE_SYS_PCIMEM_BASE
	sw	t0, MSC01_PCI_SC2PMBASL_OFS(PCI_REGS)
	sw	t0, MSC01_PCI_SC2PMMAPL_OFS(PCI_REGS)
	li	t0, (-CORE_SYS_PCIMEM_SIZE2N) & MSC01_PCI_SC2PMMSKL_MSK_MSK
	sw	t0, MSC01_PCI_SC2PMMSKL_OFS(PCI_REGS)
#undef PCI_REGS

200:
#define PCI_REGS		t2
	/* Setup PCI_SC2PIO (0x1b000000-0x1b7fffff -> 0x00000000-0x007fffff) */
	li	t0, CORE_SYS_PCIIO_BASE
	sw	t0, MSC01_PCI_SC2PIOBASL_OFS(PCI_REGS)
	sw	zero, MSC01_PCI_SC2PIOMAPL_OFS(PCI_REGS)
	li	t0, (-CORE_SYS_PCIIO_SIZE) & MSC01_PCI_SC2PIOMSKL_MSK_MSK
	sw	t0, MSC01_PCI_SC2PIOMSKL_OFS(PCI_REGS)

	/* Setup msc01 PCI_BAR0 to 256Mbyte memory window */
	li	t0, -CORE_SYS_MEMORY_SIZE
	sw	t0, MSC01_PCI_BAR0_OFS(PCI_REGS)

	/* Setup PCI_P2SC (0x00000000-0x0fffffff transparent) */
	sw	t0, MSC01_PCI_P2SCMSKL_OFS(PCI_REGS)
	sw	zero, MSC01_PCI_P2SCMAPL_OFS(PCI_REGS)

	/* Set up Vendor and device ID */
	li	t1, (PCI_VENDID_MIPS << PCI_ID_VENDORID_SHF) | \
	            (PCI_DEVID_MSC01 << PCI_ID_DEVID_SHF)
	sw	t1, MSC01_PCI_HEAD0_OFS(PCI_REGS)

	/* Set up Sub system ID and Sub system Vendor ID */
	sw	t1, MSC01_PCI_HEAD11_OFS(PCI_REGS)

	/* Set up Class code and Revision ID */
	li	t0, 0x06000001
	sw	t0, MSC01_PCI_HEAD2_OFS(PCI_REGS)
	sw	zero, MSC01_PCI_HEAD3_OFS(PCI_REGS)
	sw	zero, MSC01_PCI_HEAD4_OFS(PCI_REGS)
	sw	zero, MSC01_PCI_HEAD5_OFS(PCI_REGS)
	sw	zero, MSC01_PCI_HEAD6_OFS(PCI_REGS)
	sw	zero, MSC01_PCI_HEAD7_OFS(PCI_REGS)
	sw	zero, MSC01_PCI_HEAD8_OFS(PCI_REGS)
	sw	zero, MSC01_PCI_HEAD9_OFS(PCI_REGS)