init_platform.c

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/************************************************************************
 *
 *  init_platform.c
 *
 *  Platform specific startup code (c-code)
 *
 * ######################################################################
 *
 * mips_start_of_legal_notice
 * 
 * Copyright (c) 2004 MIPS Technologies, Inc. All rights reserved.
 *
 *
 * Unpublished rights (if any) reserved under the copyright laws of the
 * United States of America and other countries.
 *
 * This code is proprietary to MIPS Technologies, Inc. ("MIPS
 * Technologies"). Any copying, reproducing, modifying or use of this code
 * (in whole or in part) that is not expressly permitted in writing by MIPS
 * Technologies or an authorized third party is strictly prohibited. At a
 * minimum, this code is protected under unfair competition and copyright
 * laws. Violations thereof may result in criminal penalties and fines.
 *
 * MIPS Technologies reserves the right to change this code to improve
 * function, design or otherwise. MIPS Technologies does not assume any
 * liability arising out of the application or use of this code, or of any
 * error or omission in such code. Any warranties, whether express,
 * statutory, implied or otherwise, including but not limited to the implied
 * warranties of merchantability or fitness for a particular purpose, are
 * excluded. Except as expressly provided in any written license agreement
 * from MIPS Technologies or an authorized third party, the furnishing of
 * this code does not give recipient any license to any intellectual
 * property rights, including any patent rights, that cover this code.
 *
 * This code shall not be exported, reexported, transferred, or released,
 * directly or indirectly, in violation of the law of any country or
 * international law, regulation, treaty, Executive Order, statute,
 * amendments or supplements thereto. Should a conflict arise regarding the
 * export, reexport, transfer, or release of this code, the laws of the
 * United States of America shall be the governing law.
 *
 * This code constitutes one or more of the following: commercial computer
 * software, commercial computer software documentation or other commercial
 * items. If the user of this code, or any related documentation of any
 * kind, including related technical data or manuals, is an agency,
 * department, or other entity of the United States government
 * ("Government"), the use, duplication, reproduction, release,
 * modification, disclosure, or transfer of this code, or any related
 * documentation of any kind, is restricted in accordance with Federal
 * Acquisition Regulation 12.212 for civilian agencies and Defense Federal
 * Acquisition Regulation Supplement 227.7202 for military agencies. The use
 * of this code by the Government is further restricted in accordance with
 * the terms of the license agreement(s) and/or applicable contract terms
 * and conditions covering this code from MIPS Technologies or an authorized
 * third party.
 *
 *
 *
 * 
 * mips_end_of_legal_notice
 * 
 *
 ************************************************************************/


/************************************************************************
 *  Include files
 ************************************************************************/

#include <sysdefs.h>
#include <init.h>
#include <sys_api.h>
#include <syscon_api.h>
#include <pci_api.h>
#include <excep_api.h>
#include <stdio.h>
#include <product.h>
#include <malta.h>
#include <atlas.h>
#include <sead.h>
#include <core_sys.h>
#include <piix4.h>	/* Malta specific		*/
#include <superio.h>	/* Malta specific		*/

/************************************************************************
 *  Definitions
 ************************************************************************/

/* PCI access of 16 bit registers (PCI is always little endian) */
#define R16( addr )     REG16( SWAP_UINT16ADDR_EL( addr ) )

/************************************************************************
 *  Public variables (some not used here)
 ************************************************************************/

/************************************************************************
 *  Static variables
 ************************************************************************/

/* Base of PIIX4 Power Management Module (Malta only) */
static UINT32 base;

/************************************************************************
 *  Static function prototypes
 ************************************************************************/

static void
smi_isr( 
    void *data );


/************************************************************************
 *  Implementation : Public functions
 ************************************************************************/


/************************************************************************
 *
 *                          arch_platform_init
 *  Description :
 *  -------------
 *
 *  Platform specific initialisation code
 *
 *  Return values :
 *  ---------------
 *
 *  None
 *
 ************************************************************************/
void
arch_platform_init(
    bool early )	/* TRUE -> Before initmodules(), FALSE -> after */
{
    UINT32 data;
    UINT8  data8;
    volatile UINT8  *piix4_pci_io_base;

    /* TBD : Some of this may be moved to drivers (or a new "SuperIO" module) */

    if( early )
    {	
        /*  Setup variables defining the platform.
	 *  Assume that the IDs are detected using MIPS_REVISION register
         *  (special hw address reserved on Atlas, Malta, SEAD, SEAD-2 
         *  boards). If this is not the case, please modify the code.
	 */

	/*  Platform ID.
	 *  Value PRODUCT_THIRD_PARTY_ID is reserved for boards not
	 *  from MIPS Technologies.
	 */
        sys_platform = REGFIELD(REG32(KSEG1(MIPS_REVISION)), MIPS_REVISION_PROID);

	if( sys_platform == PRODUCT_THIRD_PARTY_ID )
	{
            /*  Manufacturer ID and Manufacturer's product ID */
            sys_manid = REGFIELD(REG32(KSEG1(MIPS_REVISION)), MIPS_REVISION_MANID);
            sys_manpd = REGFIELD(REG32(KSEG1(MIPS_REVISION)), MIPS_REVISION_MANPD);
	}

        /*  Core card ID.
	 *  Core cards are used on Atlas and Malta boards.
	 */
	if( (sys_platform == PRODUCT_MALTA_ID) || (sys_platform == PRODUCT_ATLASA_ID) )
	{
            sys_corecard = REGFIELD(REG32(KSEG1(MIPS_REVISION)), MIPS_REVISION_CORID);

	    if (sys_corecard == MIPS_REVISION_CORID_CORE_EMUL)
	    {
	        if (REG(MSC01_BIU_REG_BASE, MSC01_BIU_RBBASL) == CORE_SYS_REG_BASE)
		    sys_corecard = MIPS_REVISION_CORID_CORE_EMUL_SYS;
	        else
		    sys_corecard = MIPS_REVISION_CORID_CORE_EMUL_20K;
	    }
        }
	else
	    sys_corecard = MIPS_REVISION_CORID_NA;

	/* Do early platform specific initialisation
	 * (Initialisation required before YAMON modules are initialised).
	 */
        switch( sys_platform )
	{
	  case PRODUCT_SEAD2_ID :
	    /* SEAD with SOC-it 101 shares a lot of code with coreSYS */
	    /* That is achieved by setting up an artificial core card */
	    sys_corecard = 
	       (REGFIELD(REG32(KSEG1(SEAD_REVISION)), SEAD_REVISION_RTLID)
						   == SEAD_REVISION_RTLID_SOCIT101)
		? MIPS_REVISION_CORID_SEAD_MSC01
		: MIPS_REVISION_CORID_NA;
	    break;

          case PRODUCT_MALTA_ID :

            /* Perform early core specific initialisation */
	    /*  Setup Base address for PCI IO access. */
            arch_core_init( TRUE, MALTA_CPUINT_COREHI, TRUE );

            /* Enable I/O access */

            pci_config_read32( PCI_BUS_LOCAL, 
			       MALTA_DEVNUM_PIIX4,
			       PIIX4_PCI_FUNCTION_BRIDGE, 
			       PCI_SC, 
			       &data );

            pci_config_write32( PCI_BUS_LOCAL, 
			        MALTA_DEVNUM_PIIX4,
			        PIIX4_PCI_FUNCTION_BRIDGE,
			        PCI_SC, 
			        data | PCI_SC_CMD_IOS_BIT );

	    /* Select ISA mode (default is EIO) */

	    pci_config_read32( PCI_BUS_LOCAL,
			       MALTA_DEVNUM_PIIX4,
			       PIIX4_PCI_FUNCTION_BRIDGE,
			       PIIX4_PCI_GENCFG,
			       &data );

	    pci_config_write32( PCI_BUS_LOCAL,
				MALTA_DEVNUM_PIIX4,
				PIIX4_PCI_FUNCTION_BRIDGE,
				PIIX4_PCI_GENCFG,
				data | PIIX4_GENCFG_ISA_BIT );

	    /* Set top of memory accessible by ISA or DMA devices */

	    pci_config_read8( PCI_BUS_LOCAL,
			      MALTA_DEVNUM_PIIX4,
			      PIIX4_PCI_FUNCTION_BRIDGE,
			      PIIX4_PCI_TOM,
			      &data8 );

	    data8 &= ~PIIX4_TOM_TOM_MSK;
	    data8 |= PIIX4_TOM_TOM_16MB << PIIX4_TOM_TOM_SHF;

	    pci_config_write8( PCI_BUS_LOCAL,
			       MALTA_DEVNUM_PIIX4,
			       PIIX4_PCI_FUNCTION_BRIDGE,
			       PIIX4_PCI_TOM,
			       data8 );

            /**** Config mode ****/

	    piix4_pci_io_base = (volatile UINT8*)KSEG1(MALTA_PCI0_IO_BASE + PIIX4_IO_BRIDGE_START);

            MALTA_SUPER_IO8( SMSC_CONFIG_OFS ) = SMSC_CONFIG_KEY_START;


            /**** Serial port com 2 (TTY1) ****/

            /* Select device */
            MALTA_SUPER_IO8( SMSC_CONFIG_OFS ) = SMSC_CONFIG_DEVNUM;
            MALTA_SUPER_IO8( SMSC_DATA_OFS )   = SMSC_CONFIG_DEVNUM_COM2;

            /* Set base address */