msc01_memmap.h

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/* ##########################################################################
 *
 *  Default memory map
 *
 * ##########################################################################
 *
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 * Copyright (c) 2004 MIPS Technologies, Inc. All rights reserved.
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 * Unpublished rights (if any) reserved under the copyright laws of the
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 * This code is proprietary to MIPS Technologies, Inc. ("MIPS
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 * (in whole or in part) that is not expressly permitted in writing by MIPS
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 */

#ifndef MSC01_MEMMAP_H
#define MSC01_MEMMAP_H

#ifndef KSEG1_BASE
# define KSEG0_BASE      	0x80000000	/* unmapped, cachable	*/
# define KSEG1_BASE      	0xa0000000	/* unmapped, uncached	*/
#endif

/*****************************************************************************
 * IPIF generic register space addresses, unmapped & uncached access via kseg1
 ****************************************************************************/

#define	MSC01_REGSPACE_MC	0
#define	MSC01_REGSPACE_IC	1
#define	MSC01_REGSPACE_BIU	2
#define	MSC01_REGSPACE_IP1	3
#define	MSC01_REGSPACE_IP2	4
#define	MSC01_REGSPACE_IP3	5

#define	MSC01_REGADDR_RESET	(KSEG1_BASE + 0x1f800000) /* power-up value */
#define	MSC01_REGADDR_SIZE	0x00040000		  /* 256 KByte	    */
#define	MSC01_REGADDR(regspace)	(MSC01_REGADDR_BASE	\
				 +(regspace)*MSC01_REGADDR_SIZE)



/*****************************************************************************
 * Default register base addresses (can be modified at run-time by software)
 ****************************************************************************/

#define	MSC01_REGADDR_BASE	(KSEG1_BASE + 0x1bc00000) /* programmed val */

#define MSC01_MC_REG_BASE	MSC01_REGADDR(MSC01_REGSPACE_MC)
#define MSC01_IC_REG_BASE	MSC01_REGADDR(MSC01_REGSPACE_IC)
#define MSC01_BIU_REG_BASE	MSC01_REGADDR(MSC01_REGSPACE_BIU)
#define MSC01_SC_REG_BASE	MSC01_REGADDR(MSC01_REGSPACE_BIU)
#define MSC01_IP1_REG_BASE	MSC01_REGADDR(MSC01_REGSPACE_IP1)
#define MSC01_IP2_REG_BASE	MSC01_REGADDR(MSC01_REGSPACE_IP2)
#define MSC01_IP3_REG_BASE	MSC01_REGADDR(MSC01_REGSPACE_IP3)


/*****************************************************************************
 * Power-up memory space (can be modified at run-time by software)
 ****************************************************************************/

#define	MSC01_PHYSBASE_MC	0x00000000
#define	MSC01_PHYSBASE_IP1	0x10000000
#define	MSC01_PHYSBASE_IP2	0x14000000
#define	MSC01_PHYSBASE_IP3	0x18000000

#define	MSC01_KSEG0BASE_MC	(KSEG0_BASE + MSC01_PHYSBASE_MC)
#define	MSC01_KSEG0BASE_IP1	(KSEG0_BASE + MSC01_PHYSBASE_IP1)
#define	MSC01_KSEG0BASE_IP2	(KSEG0_BASE + MSC01_PHYSBASE_IP2)
#define	MSC01_KSEG0BASE_IP3	(KSEG0_BASE + MSC01_PHYSBASE_IP3)

#endif